一些IC前端设计工具

可紊 提交于 2019-11-28 02:37:17
一些IC前端设计工具
 

 (1)代码输入:
           语言输入:    Summit VisualHDL                Summit
                                  Renior                                 Mentor
           图形输入:    composer                            Candence
                                  Viewlogic                             Viewdraw
     (2)电路仿真:数字电路仿真
                                  Verilog:
                                  VCS                                     Synopsys
                                  Verilog—XL                          Candence
                                  modle-sim                            Mentor
                                  Vhdl:
                                   VSS                                    Synopsys
                                   NC—vhdl                            Candence
                                   modle-sim                           Mentor
                                模拟电路仿真                                 
                                   Hsipce                                                 Synopsys
                                   Spectre Simulator ,Pspice                 Cadence
                                   SmartSpice                                          Silvaco
(3)逻辑综合:
                                 DC Expert                            Synopsys
                                 BuilderGates                         Cadence
                                 Blaster RTL                           Magama
                                 Synplify   PRO                       Synplify

转载于:https://www.cnblogs.com/asic/archive/2011/05/22/2053414.html

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