VHDL with select when error

问题

VHDL is the worst designed language with the worst syntax that I have ever encountered. Why does this with-select-when code give me an error?:

  library ieee;
use ieee.std_logic_1164.all;

entity mux48 is
port(
   mux48dv0:in std_logic_vector(7 downto 0);
   mux48dv1:in std_logic_vector(7 downto 0);
   mux48dv2:in std_logic_vector(7 downto 0);
   mux48dv3:in std_logic_vector(7 downto 0);
   mux48sv:in std_logic_vector(3 downto 0);
   mux48ov:out std_logic_vector(7 downto 0)
);
end mux48;

architectre mux48_df of mux48 is
begin
    with mux48sv select
    mux48ov <= mux48dv0 when "0000",
        <= mux48dv1 when "0001",
        <= mux48dv2 when "0010",
        <= mux48dv3 when "0011",
        <= mux48dv0 when "0100",
        <= mux48dv1 when "0101",
        <= mux48dv2 when "0110",
        <= mux48dv3 when "0111",
        <= mux48dv0 when "1000",
        <= mux48dv1 when "1001",
        <= mux48dv2 when "1010",
        <= mux48dv3 when "1011",
        <= mux48dv0 when "1100",
        <= mux48dv1 when "1101",
        <= mux48dv2 when "1110",
        <= mux48dv3 when "1111";
end mux48_df;

error:

** Error: C:/Modeltech_pe_edu_10.3/Lab3/mux48.vhd(15): near "architectre": syntax error

回答1:

You have several syntax errors: The assignment should look like

with mux48sv select
   mux48ov <= mux48dv0 when "0000",
              mux48dv1 when "0001",
              ...
              mux48dv3 when others;

来源：https://stackoverflow.com/questions/21588740/vhdl-with-select-when-error