BCM2708 (RPi) Rasbpian FIQ not triggered

问题

I have written a Linux Loadable Kernel Module which attempts to attach to the FIQ to service GPIO edge transistions. The Pin in question is on GPIO0 (IRQ 49) so I attempt to configure the FIQ as follows:

#ifndef GPIO_BASE
#define GPIO_BASE       0x7E200000
#endif
#define GPIO_LEN        0x60
#define GPIO_GPEDS0     0x10
#define GPIO_GPEDS1     0x11
#define GPIO_GPREN0     0x13
#define GPIO_GPREN1     0x14
#define GPIO_GPFEN0     0x16
#define GPIO_GPFEN1     0x17

#define AIR_BASE    0x7E00B200
#define AIR_LEN     0x28
#define AIR_IP2     2    // IRQ pending source 63:32
#define AIR_FIQ     3    // FIQ Config register
#define AIR_FIQ_AN  0x80L   //      FIQ enable field mask
#define AIR_FIQ_SRC 0x7FL   //      FIQ Source field mask
#define AIR_EN2     5    // IRQ Enable IRQ source 63:32
#define AIR_DE2     8    // IRQ Disable IRQ source 63:32

#define AIR_GPIO0_IRQ   49

struct {
    uint32_t wr_p;       
} fiq_data_s;

extern unsigned char pulse_logger_fiq_handler, pulse_logger_fiq_handler_end;

static struct fiq_handler pulse_logger_fh = {
    .name   = "pulse_logger_fiq_handler"
};

static int __init pulse_logger_init(void)
{
    gpioReg = ioremap(GPIO_BASE, GPIO_LEN);
    aircReg = ioremap(AIR_BASE, AIR_LEN);
    fiq_data_s.wr_p  = (uint32_t)&wr_p;                         // Log offset to store system counter

    printk(KERN_INFO "Enabling FIQ...\n");

    printk(KERN_INFO "\tdisable GPIO0 IRQ\n");
    // Disable IRQ tied to FIQ
    disable_irq_nosync(AIR_GPIO0_IRQ);

    printk(KERN_INFO "\tConfig GPIO Edge Events\n");
    writel(AIR_GPIO0_MSK, gpioReg + GPIO_GPEDS0);
    gpren0 = readl((const volatile void *)(gpioReg + GPIO_GPREN0));
    gpren0 |= AIR_GPIO0_MSK;
    writel(gpren0, gpioReg + GPIO_GPREN0);
    gpfen0 = readl((const volatile void *)(gpioReg + GPIO_GPFEN0));
    gpfen0 |= AIR_GPIO0_MSK;
    writel(gpfen0, gpioReg + GPIO_GPFEN0);

    printk(KERN_INFO "\tClaim FIQ\n");
    // Reserve the FIQ
    ret = claim_fiq(&pulse_logger_fh);
    if (ret){
        printk(KERN_INFO "Failed to claim FIQ (%d)!\n", ret);
        goto fail1;
    }

    // Copy FIQ to vector location
    printk(KERN_INFO "\tcopying handler\n");
    set_fiq_handler(&pulse_logger_fiq_handler,
            &pulse_logger_fiq_handler_end - &pulse_logger_fiq_handler);

    // Store symbol pointers in FIQ registers
    printk(KERN_INFO "\tstoring registers\n");
    memset(&regs,0, sizeof(regs));
    regs.ARM_r8  = (long)&fiq_data_s;
    set_fiq_regs(&regs);

    printk(KERN_INFO "\tEnable FIQ\n");
    // Enable the FIQ
    enable_fiq(AIR_GPIO0_IRQ);
    local_fiq_enable();

    return 0;
}

I then find that the FIQ register has an invalid entry of 0x54 so I force the FIQ register:

writel(0x80 | AIR_GPIO0_IRQ, (volatile void *)(aircReg + AIR_FIQ));

I have written the FIQ as follows:

#define DATA_ACK_OFFSET     12

ENTRY(pulse_logger_fiq_handler)
        /* Acknowledge the interrupt */
        /* Write PIN_ACK to the EVENT_STATUS_OFFSET register */
        LDR R14, [R8, #DATA_ACK_OFFSET]     /* Load Address */
        MOV R12, #PIN_ACK
        STR R12, [R14, #0]

        LDR R14, [R8, #0]   /* Load Address */
        LDR R14, [R14, #0]  /* Load Value */
        ADD R14, R14, #1
        LDR R12, [R8, #0]   /* Load Address */
        STR R14, [R12, #0]

        /* return from fiq */
        subs  pc, lr, #4
pulse_logger_fiq_handler_end:

I then toggle the line 20 times (using another GPIO) but at the end of the run wr_p == 1.

If I run the code as a standard ISR wr_p == 20, leaving me to believe that the ISR code is valid, I just need to understand why the FIQ only appears to be firing once.

static irqreturn_t pulse_isr(int irq, void *data)
{
    uint32_t fiq_data_addr = (uint32_t)&fiq_data_s;
    *((uint32_t*)*((uint32_t*)fiq_data_addr)) += 1;

    __asm__ __volatile__ (
        "MOV R8,  %[fiqbase]    \n"

        "LDR R14, [R8, #12]    \n\t"     /* Load Address */
        "MOV R12, #0x00000010    \n\t"
        "STR R12, [R14, #0]    \n\t"

        "LDR R14, [R8, #0]    \n\t"/* Load Address */
        "LDR R14, [R14, #0]                  \n\t"/* Load Value */
        "ADD R14, R14, #1                    \n\t"
        "LDR R12, [R8, #0]    \n\t"   /* Load Address */
        "STR R14, [R12, #0]                  \n\t"
        :: [fiqbase] "r" (fiq_data_addr)
        : "r8", "r12", "r14");
    return IRQ_HANDLED;
}

If I dig in to [local_]enable_fiq() it doesn't look like it touches the hardware at all which is why I think I have to write the register but, I don't see this happening in other drivers that I have looked at online so I'm confused.

Is there a reason why this would only be triggering once (even if I don't write the FIQ register)?

回答1:

I figured it out, r13-r14 are not actually general purpose registers. These are the SP and LR.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337h/Chdedegj.html

A rewrite to use r8-r12 has this working.

来源：https://stackoverflow.com/questions/32194264/bcm2708-rpi-rasbpian-fiq-not-triggered

标签

assembly

linux-kernel

embedded

raspbian