问题
I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else):
- Generate .rbf file.
- I made a preloader using the bsp-editor tool from EDS-SoC.
- Compile successfully the preloader and obtain preloader-mkpimage.bin.
- Generate uboot and also uboot script file.
- Load preloader into SD card using alt-boot-disk-util.
- Copy all the rbf file, uboot and uboot script to an SD card. At this moment I did not make any application because I wanted to check if the preloader loaded or not.
- Plug SD card into the board and then power up 8. In Putty, I saw the U-boot spl and Uboot worked fine.
With the first success, I tried to make my own HPS-FPGA design. I based on HPS configuration to make my own HPS ( initialize I2C, UART, no sdram, etc. ). For the FPGA part, I put some LEDs PIO, JTAG UART, System ID peripheral, etc.
After finish my Platform designer ( Qsys), I made a VHDL top file and connect all the nodes ( just like GSRD design). At this point, I did not add any IP such as HPS reset, debounce, etc. because I just wanted to see if the preloader worked or not.
Then I followed exactly those steps as I did with GSRD design, however this time on Putty I received nothing. U-Boot SPL did not even appear. Feeling weird, I came back to GSRD to check. I copied the whole folder of GSRD design and made it my own new project. Then I launched an update for those IP and compiled the whole thing again. After that, preloader and uboot were made in the same steps and the result amazed me: On Putty terminal, I only had this single line
U-Boot SPL 2013.01.01 (Mar 08 2019 - 10:28:04)
and nothing else happened. I think that something wrong with the preloader, it has something mismatched with my Quartus design or I have made mistakes during building the preloader.
I have searched in a lot of places, came up with many hypotheses, and tried to fix this. I even contacted Terasic and visited the Intel community forum, but I still haven't got an answer.
回答1:
If U-boot is not showing up, then the preloader is not doing its job. There are some settings that you need to check when building the preloader for baremetal designs (Watchdog timer must be disabled for instance).
If U-boot starts and you can enter commands in it it means your preloader works fine. You could enter commands manually on u-boot at first to configure the FPGA (enable bridges, load rbf and go to the software application start address) If by following this method you get the application and FPGA running, it means all your files are correctly generated but you need to script the necessary u-boot commands and run the script to automatically configure the FPGA and run the application from u-boot.
Here is a link to a github repository for DE1-SoC where you can find a full tutorial on how to boot HPS-FPGA system in baremetal : https://github.com/sahandKashani/SoC-FPGA-Design-Guide/blob/master/DE1_SoC/SoC-FPGA%20Design%20Guide/SoC-FPGA%20Design%20Guide%20%5BDE1-SoC%20Edition%5D.pdf
I hope it helps!
来源：https://stackoverflow.com/questions/55060929/atlas-soc-board-preloader-troubleshooting