Verilog Testbench Clock

问题

I have tried this multiple ways, I am a bit desperate now. I have tried to make this clock in my testbench the problem is in simulation it doesn't work or my simulation seems to freeze. I know it has to be the clock.

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
    end
end
initial begin 
    reset = 0; 
    #15 L = 0; R = 0; H = 0;        
    #20 L = 0; R = 0; H = 1;
    #25 L = 0; R = 1; H = 0;
    #30 L = 0; R = 1; H = 1;
    #35 L = 1; R = 0; H = 0;
    #45 L = 1; R = 0; H = 1;
    #50 L = 1; R = 1; H = 0;
    #55 L = 1; R = 1; H = 1;

    reset = 1; 
    #60 L = 0; R = 0; H = 0;        
    #65 L = 0; R = 0; H = 1;
    #70 L = 0; R = 1; H = 0;
    #75 L = 0; R = 1; H = 1;
    #80 L = 1; R = 0; H = 0;
    #85 L = 1; R = 0; H = 1;
    #90 L = 1; R = 1; H = 0;
    #95 L = 1; R = 1; H = 1;
    $stop ; 
 end

endmodule

回答1:

 initial begin 
    forever begin
    clk = 0;
    #10 clk = ~clk;
 end end

Try moving clk=0 above the forever loop. Instead of toggling the clock every #10 you're resetting the clock to 0 every #10 units, and then toggling it instantly. I think that still might work in some cases, but it's probably not what you intended to do.

回答2:

for clock simply use

parameter PERIOD = 10; //whatever period you want, it will be based on your timescale

always #PERIOD clk=~clk; //now you create your cyclic clock

//==//

More complete:

module testbench;
timeunit 1ns;
timeprecision 100ps;
initial begin
  $display($time, " << Starting the Simulation >>");
    rstn = 1'b0;
    clk = 0;
    #5 rstn = 1'b1;
end

always #PERIOD clk=~clk;


initial
begin
      $dumpfile("your_choice_of_name.vcd");
      $dumpvars;
end

initial
begin
//whatever you come up
end

endmodule

回答3:

Or simply just do this ..

 initial begin 
        reset = 0; clk = 0;
        #15 L = 0; R = 0; H = 0;        
        #20 L = 0; R = 0; H = 1;
        #25 L = 0; R = 1; H = 0;
        #30 L = 0; R = 1; H = 1;
        #35 L = 1; R = 0; H = 0;
        #45 L = 1; R = 0; H = 1;
        #50 L = 1; R = 1; H = 0;
        #55 L = 1; R = 1; H = 1;

        reset = 1; 
        #60 L = 0; R = 0; H = 0;        
        #65 L = 0; R = 0; H = 1;
        #70 L = 0; R = 1; H = 0;
        #75 L = 0; R = 1; H = 1;
        #80 L = 1; R = 0; H = 0;
        #85 L = 1; R = 0; H = 1;
        #90 L = 1; R = 1; H = 0;
        #95 L = 1; R = 1; H = 1;
        $stop ; 
     end 

always 
   #10 clk = ~clk;

来源：https://stackoverflow.com/questions/24924956/verilog-testbench-clock

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verilog

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