问题
I am trying to get the Xilinx AXI IIC-Core example to work, which can be found at C:\Xilinx\14.7\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\iic_v2_08_a\examples\xiic_slave_example.c. Has anyone experiences with this core?
I found this pg090 axi iic description, which says that
Standard communication on the bus between a master and a slave is composed of four parts:
- START
- Slave Address
- Data Transfer
- STOP
But when I transmit an write transfer, both address and message where accepted but SCL is kept low by the SLAVE.
Could anyone give me a hint why this occurs? Although a detailed description of the timing characteristics could be helpful.
回答1:
Very late answer I know and not really an answer exactly but I have tried this example with the same results. The reason why it probably stays low is because the example expects a certain number of bytes to be received, which in the real world isn't practical at all for a typical slave device.
I managed to implement a working slave with a typical "EEPROM" protocol without the use of interrupts by using low level functions only (defines in xiic_l.h) and reading the AXI IIC Bus Interface v2.0 documentation page 34-35.
The example code is most likely caused by an unhandled interrupt or not clearing an interrupt when it should in one of the handlers, never found out which one though. It's probably waiting for RX_FIFO_PIRQ to be reached which as I said is impractical for a slave, it should be bit by bit, which is why RX_FIFO_PIRQ should be 0x00.
some things I've learned. CTRL.TX must be 1 to transmit from slave, and CTRL.TXFIFORESET must be 0 before transmit can be written (I had this high to clear and it didn't auto reset the bit then write to TX did nothing i.e. SCL/SDA low)...
I'm going to make a start on an interrupt version to see how it can be implemented with interrupts.
来源：https://stackoverflow.com/questions/30798620/xilinx-axi-iic-slave-protocol-description