问题
On MIPS architecture with pipelining and forwarding:
add $s0, $t1, $t2
sw $s0, 0($sp)
The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read).
There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls:
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1,$t2
sw $t3, 12($t0)
lw $t4, 8($01)
add $t5, $t1,$t4
sw $t5, 16($t0)
Solution:
lw $t1, 0($t0)
lw $t2, 4($t1)
lw $t4, 8($01)
add $t3, $t1,$t2
sw $t3, 12($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
In the solution it correctly recognizes the load-use hazard and rearranges the code accordingly, but is there an execute-store hazard as well?
回答1:
Let's consider a MIPS in which forwarding is activated.
I think that in that case no hazard occurs: in fact the ADD instruction is an integer operation that in the MIPS architecture requires only one clock cycle.
Look at this graph:
ADD $t3,$t1,$t2 IF ID EX MEM WB
SW $t3,12($t0) IF ID EX MEM WB
As you can see no hazard occurs because the SW instruction stores the datum after two clock cycles since the result is put in $t3 by ADD.
Actually in similar situations a hazard can occur but only if the unit is a multicycle one (if it requires more than one clock cycle to compute the data). Look ad this example, in which the ADD.D instruction uses a floating point adder that requires 4 clock cycles to perform the calculation:
ADD.D F2,F4,F5 IF ID A0 A1 A2 A3 MEM WB
S.D F2,somewhere IF ID EX X0 X1 X2 MEM WB
X0 and X1 are RAW stalls while X2 is a structural stalls: in the former case S.D must wait for ADD.D to finish; in the latter your MIPS cannot access in the same clock cycle to the memory two times, so a structural stall occurs.
来源：https://stackoverflow.com/questions/30633283/is-there-an-execute-store-data-hazard-in-mips