ARM GIC | 易学教程

GIC 简介

GIC 的全称为 General Interrupt Controller，主要作用可以归结为：
接受硬件中断信号并进行简单处理，通过一定的设置策略，分给对应的CPU进行处理。

Terminology

IRI: Interrupt Routing Infrastructure. The Distributor, Redistributor and ITS are collectively known as an IRI.
     The IRI performs interrupt grouping, interrupt prioritization, and controls the forwarding of interrupts
     to the CPU interfaces.
ITS: Interrupt translation service, is an OPTIONAL hardware mechanism in the GICv3 architecture that routes
     LPIs to the appropriate Redistributor, and the GICv4  implementations must include at least one ITS.

ARM 中断源分类

SGI: Software Generated Interrupt
软件产生中断，中断号是0-15。通过向SGI寄存器写数触发，相当于IPI，可用于CPU间的通信，比如时间同步，全局进程调度信息等。The Redistributor provides the configuration settings for PPIs and SGIs.
PPI: Private Peripheral Interrupt
私有外设中断，中断号是16~31。这些中断一般是发送给特定的CPU的，比如每个CPU有自己对应的Physical timer，产生的中断信号就发送给这个特定的CPU进行处理。The Redistributor provides the configuration settings for PPIs and SGIs.
SPI: Shared Peripheral Interrupt
共享外设中断，一般定义的硬件中断号范围32~1019。比如按键触发一个中断，手机触摸屏触发的中断，共享的意思是说可以发送给多个CPU或者说Core处理，不限定特定的CPU。The Distributor provides the routing configuration for SPIs, and holds all the associated routing and priority information.
特殊中断号。1020-1023。
保留中断号，1024-8191。
LPI: Locality-specific Peripheral Interrupt
局部外设中断，中断号 >=8192 。LPI没有Active状态，得到响应后由处理器自动转入inactive状态。这是一个基于消息的中断类型，是ARM为后续的SERVER等产品做的扩展。
LPIs are new in GICv3, and they are different to the other types of interruptin a number of ways . In particular, LPIs are always message-based interrupts,and their configuration is held in tables in memory rather than registers.
在传统的GIC流程中如上图，外围设备的中断触发线是引出到GIC上的，这样可以理解为一个物理的SIGNAL，比如一个高电平信号，边沿触发信号。实际上在现在GIC_V3中，中断可以依照 MESSAGE BASED 方式来触发，外围设备的中断信号先到 Interconnect(AMBA总线)，然后片上总线再给 GIC 发送一个消息，这个作为一个 IRQ 来源。

Affinity Route

SPIs are routed using an affinity address and the routing mode information that is held in `GICD_IROUTER<n>`.
SGIs are routed using the affinity address and routing mode information that is written by software when it
generates the SGI.

SGIs are generated using the following registers:
• ICC_SGI0R_EL1.
• ICC_SGI1R_EL1.
• ICC_ASGI1R_EL1.

irq 的生命周期

State	Details
inactive	An interrupt that is not active or pending
pending	An interrupt that is waiting to be serviced by a target processor
active	An interrupt that has been acknowledged by a processor and is being serviced but has not completed
active and pending	A processor is servicing the interrupt and the GIC has a pending interrupt from same source

GIC V3 结构

在这里插入图片描述

The Distributor provides the routing configuration for SPIs, and holds all the associated routing and priority.
The Redistributor provides the configuration settings for PPIs and SGIs. A Redistributor always presents the pending interrupt with the highest priority to the CPU interface in finite time.

Distributor

The Distributor performs interrupt prioritization and distribution of SPIs and SGIs to the
Redistributors and CPU interfaces that are connected to the PEs in the system.
GICD_CTLR provides global settings for:
• Enabling affinity routing.
• Disabling security.
• Enabling Secure and Non-secure Group 1 interrupts.
• Enabling Group 0 interrupts.

For SPIs, the Distributor provides a programming interface for:
• Enabling or disabling SPIs.
• Setting the priority level of each SPI.
• Routing information for each SPI.
• Setting each SPI to be level-sensitive or edge-triggered.
• Generating message-based SPIs.
• Assigning each SPI to an interrupt group.
• Controlling the pending and active state of SPIs.

The Distributor registers are identified by the GICD_ prefix.

对所有 CPU 都有效，主要控制 SPI 的相关属性。

CPU interface

Each Redistributor is connected to a CPU interface.
The CPU interface provides a programming interface for:
• General control and configuration to enable interrupt handling in accordance with the
  Security state and legacy support requirements of the implementation.
• Acknowledging an interrupt.
• Performing a priority drop.
• Deactivation of an interrupt.
• Setting an interrupt priority mask for the PE.
• Defining the preemption policy for the PE.
• Determining the highest priority pending interrupt for the PE.

对各个 CPU 有效，控制中断是否上报，中断 ack，屏蔽，抢占等。

Redistributor (GIC_v3, v4)

For each connected PE there is a Redistributor.
Redistributors provide a programming interface for:
• Identifying, controlling, and configuring supported features to enable interrupts and
  interrupt routing of the implementation.
• Enabling or disabling SGIs and PPIs.
• Setting the priority level of SGIs and PPIs.
• Setting each PPI to be level-sensitive or edge-triggered.
• Assigning each SGI and PPI to an interrupt group.
• Controlling the pending state of SGIs and PPIs.
• Controlling the active state of SGIs and PPIs.
• Power management support for the connected PE.
• Where LPIs are supported, base address control for the data structures in memory that
  support the associated interrupt properties and their pending status.
• Where GICv4 is supported, base address control for the data structures in memory
  that support the associated virtual interrupt properties and their pending status.

The Redistributor registers are identified by the GICR_ prefix.

对各个 CPU 有效，主要控制 SGI 和 PPI 的属性。

IRQ Group

中断产生被送到哪个异常级、安全域还是非安全域处理，这些也是在 GIC 里进行配置。

In a system with two Security states, an interrupt is configured as one of the following:
A Group 0：ARM expects these interrupts to be handled at EL3.
A Secure Group 1：ARM expects these interrupts to be handled at Secure EL1.
A Non-secure Group 1：ARM expects these interrupts to be handled at Non-secure EL2 in systems using virtualization,
                      or at Non-secure EL1 in systems not using virtualization.

In a system with one Security state an interrupt is configured to be either:
• Group 0.
• Group 1.

GICD_IGROUPR<n> and GICD_IGRPMODR<n> configure the interrupt group for SPIs. n is greater than zero.
GICR_IGROUPR0 and GICR_IGRPMODR0 configure the interrupt group for SGIs and PPIs.

由 GICD_CTLR.DS 位控制。开启两个安全态时会在中断 configure, ack, priority drop, deactivation 中进行安全态检查。

When GICD_CTLR.DS == 0, LPIs are always Non-secure Group 1 interrupts.
When GICD_CTLR.DS == 1, LPIs are always Group 1 interrupts.

When GICD_CTLR.DS == 0
• The GIC supports two Security states, Secure state and Non-secure state.
• The GIC supports three interrupt groups:
— Group 0.
— Secure Group 1.
— Non-secure Group 1.
这个时候 Group 0 中断始终是安全态的，非安全态下无法访问 Group 0 相关的寄存器。

When GICD_CTLR.DS == 1:
• The GIC supports only a single Security state. This can be either Secure state or Non-secure state.
• The GIC supports two interrupt groups:
— Group 0.
— Group 1.

IRQ & FIQ

最终中断都会被归类到 ARMv8 的 FIQ 或 IRQ。这个和中断发生时处理器所在的异常级、安全态以及中断所属的 Group 相关。
这里不再详述，可参阅数据手册。

Interrupt Prioritization

数值越小优先级越高，即 0 优先级最高。优先级是 8-bit 无符号数字，实际实现可以采用更少的 bits 来表示，此时相当于优先级分组，比如只用了高 4-bit 来表示，低4-bit将被忽略，那么原来的 256 个优先级变成了 16个优先级，原来 0-15 都映射到了 0 优先级上。In a multiprocessor implementation, ICC_CTLR_EL1.PRIbits and ICC_CTLR_EL3.PRIbits indicate the number of priority bits implemented, independently for each target PE.
GICD_IPRIORITYR<n> 控制每个 SPI 的优先级。
GICR_IPRIORITYR<n> 控制每个 SGI 和 PPI 的优先级。

The Binary Point Registers split a priority value into two fields, the group priority and the subpriority. When
determining preemption, all interrupts with the same group priority are considered to have the same priority,
regardless of the subpriority.

Interrupt lifecycle

主要描述 ack -> priority drop -> deactive

Activation

通过以下寄存器可以获取当前在PE上被触发的中断号，读操作会转移中断的状态到 active。
The interrupt handler reads ICC_IAR0_EL1 for Group 0 interrupts, and ICC_IAR1_EL1 for Group 1 interrupts.
This read acts as an acknowledge for the interrupt. The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a returned INTID are not guaranteed to be visible until after the execution of a DSB.

Priority drop

After an interrupt has been acknowledged, a valid write to ICC_EOIR0_EL1 for Group 0 interrupts, or a valid write to ICC_EOIR1_EL1 for Group 1 interrupts, results in a priority drop. It is required for each acknowledged interrupt, even for LPIs which do not have an active state. A priority drop must be performed by the same PE that activated the interrupt.
值得注意的是，写 EOI 寄存器的顺序和读 IAR 寄存器的顺序必须是严格相反的。

Deactive

PPIs, SGIs, and SPIs have an active state in the IRI and must be deactivated.
SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a different PE.
Interrupt deactivation is required to change the state of an interrupt either:
• From active and pending to pending.
• From active to inactive.

GIC V3 的初始化

Interrupt Controller中的 Distributor, Redistributor, CPU Interface 需要按照不同顺序配置。Distributor是所有CPU都可以对应的，那么这个只要在第一个CPU启动时配置就可以了，对于 Redistributor 和 CPU Interface 是 PER-CPU 对应的，所以在 SECONDARY CPU 启动时候需要配置各自的组件。