what does 3'bzzz stands for in verilog?

问题

I have the following code but I don’t know what the 3'bzzz stands for:

`timescale 1ns / 1ps
module reg_tercer_estado(entrada,hab,salida);
input [2:0] entrada;
input hab;
output [2:0] salida;
reg [2:0] auxsalida;

always @(entrada)
begin
    case (hab)
    1'b0: auxsalida=entrada;
    1'b1: auxsalida=3'bzzz;
    endcase
end

assign salida=auxsalida;

endmodule

回答1:

According to “HDL Compiler for Verilog” manual, 3'bzzz is 3-bit number, and z is a condition for 'disconnected' or 'high impedance', and it's also is not synthesizable.

So, 3'bzzz means a 3-bit value with all three bits in disconnected state.

来源：https://stackoverflow.com/questions/23453533/what-does-3bzzz-stands-for-in-verilog