问题
Is there any way to read the CPU cache contents? Architecture is for ARM.
I m invalidating a range of addresses and then want to make sure whether it is invalidated or not. Although I can do read and write of the range of addresses with and without invalidating and checking the invalidation, I want to know whether it is possible to read the cache contents
Thanks!!
回答1:
ARM9 provides cache manipulation and test registers that allow you to examine the state of the cache. Here's a reasonable starting point:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0151c/Chdcfejb.html
The ICache and DCache are maintained using MCR and MRC instructions to CP15 registers 7 and 9, defined by the ARM v4T programmer’s model. Additional operations are available using MCR and MRC to CP15 register 15. These operations are combined with those using registers 7 and 9 to enable testing of the caches entirely in software.
These are privileged instructions so they may not be accessible on your target platform.
I'd start with a simple program that dumps the state of all the cache lines. That should give you enough information to read the data in the cache simply by reading the memory locations the cache tags provide.
回答2:
I'm hesitant to write it's impossible, so I'm writing it's extremely hard. There is probably no generic answer. given that CPU cache works transparently it's not possible to read its content from attached CPU without altering cache content. CPU caches are usually implemented as CAM (content addressable memory, associative memory) if CPU tries to access data, the cache is looked up, if data are not there they are fetched from memory, but I'm afraid this process is transparent to CPU.
The option is to use a kind of HW observation module and sniff on system bus, which connects cache to RAM. If the request for data would appear on bus, then the requested data were not in cache.
hope someone with deeper HW knowledge will shed a light.
there is an entry on wikipedia discussing CPU caching: http://en.wikipedia.org/wiki/CPU_cache
回答3:
By definition, all you would need to do to read a cache content would be to load the memory location being stored by the cache. If the cache is working properly, it would extract the content from cache.
However, if you're trying to read the content of the I-cache, that is architecturally dependent. Plus, you will have race conditions to consider. The instruction for reading a cache content may inadvertently over-write the cache content itself.
回答4:
As stated in this thread, simply using the CPU can cause the contents of cache to change. Since (most) cache implementations are intentionally completely transparent to the CPU, you will not be able to view the contents of the cache directly from within software running on traditional CPUs.
To do something like this would require either a cache-aware CPU (with special instructions for controlling the cache; I have no idea if these really exist), or you would need to install a separate HW module to view the cache. Here are 2 ideas I have for that:
Replace your original cache controller with one that has additional control features and can be connected to the system bus to read data. This controller sits "between" the CPU and cache.
Place a secondary module in parallel with the original cache, with read-only cache access. Using a special interrupt line (or similar hardware -NOT- software signal), the CPU could then trigger a dump of the cache into this module's memory, and then read it back (over a bus) later. This controller would not affect the operation of your cache; it would simply allow you to take snapshots at any given time.
来源：https://stackoverflow.com/questions/1006981/read-cpu-cache-contents