问题
I am programming with Xilinx's vivado in verilog.
I was wondering why for some outputs we use reg
For example reg [3:0] encoder_output
we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to "STORE SOMETHING"
Is my idea right??
回答1:
It's not actually a stupid question, despite all the downvotes. In The Beginning, The Designer created nets and registers. Nets were intended as connections between hardware elements, and had values driven onto them; they didn't hold those values. Nets are normally declared as wire. Registers were data storage elements, and did hold a value; they are normally declared as reg. Over time, it became clear that this division (which sort-of-looks-like "hardware") doesn't make sense, and at least one proposal was made to drop the net/register distinction from the language. This never happened (unless you consider SystemVerilog to be 'Verilog', which I don't).
So, your question made sense 30 years ago, and your answer would have been "correct".
However, in practice, it doesn't matter which you use. The real distinction is that you can only assign to a reg from within sequential code (always/etc), and to a wire otherwise. This requirement is completely arbitrary and only exists for historical reasons. You just need to learn the rules.
来源：https://stackoverflow.com/questions/33485197/why-do-we-use-reg-in-fgpa-vhdl-vivado