问题
The interrupt based UART IO allows the data transfer to take place without intervention of CPU. Now the question is, if not CPU who controls this ? Is it the DMA controller or some external master who gets the control over memory bus from CPU. Didn't get a proper answer here . If it is the DMA controller then what makes DMA and interrupt based transfer different
回答1:
Didn't get a proper answer here .
If it is the DMA controller then what makes DMA and interrupt based transfer different
That question didn't get any good answers IMO, because the question has faulty wording.
In fact I don't understand his description of "Interrupt-driven" because it makes no sense, and it's not because I lack knowledge/experience in this area.
"DMA" is not the alternative to "interrupts".
Instead they are orthogonal concepts, and both concepts are typically used together.
The alternative to DMA is programmed I/O, aka PIO.
The alternative to interrupts is polling.
DMA transfers almost alway employ a completion interrupt (from the DMA controller) to notify the CPU that a buffer transfer is complete.
PIO often uses an interrupt (from the device) to initiate each byte/word data transfer. This helps mitigate the CPU-intensive nature of PIO. A polled PIO transfer would otherwise totally consume CPU resources.
But to refer to "PIO with interrupts" as simply "interrupts" is inaccurate and misleading.
The interrupt based UART IO allows the data transfer to take place without intervention of CPU. Now the question is, if not CPU who controls this ?
You have not specified the source of the interrupt; therefore your question is ambiguous.
If "interrupt based" is supposed to refer to "PIO with interrupt from UART", then the question makes no sense at all, since it is the CPU that is in control of the transfer.
If "interrupt based" is supposed to refer to a DMA transfer with interrupts from the DMA controller, then you are using these terms in a context not previously used in your or the linked questions.
For a UART read:
In a DMA transfer, each byte is read from the UART (when the UART signals that data is available), and written to memory by the DMA controller. The DMA controller has to be setup to perform this task. While the DMA controller oversees this transfer, the CPU will be executing other (presumably unrelated) instructions (e.g. for another process).
In a PIO transfer the CPU is in control the entire time, executing instructions to read from the device and writing to memory.
Is it the DMA controller or some external master who gets the control over memory bus from CPU.
The memory bus is maintained by the memory controller. No other device gets control of the memory bus.
To actually read from or write to memory it is the DMA controller that requests access to memory during a DMA transfer.
Note that there are privileged devices, such as a bus master or coprocessor/GPU, that can also request access to memory.
But the CPU is typically assigned the highest priority for memory access.
来源：https://stackoverflow.com/questions/38119491/master-for-interrupt-based-uart-io