gate level parsing using yosys

问题

I want to parse the following sequential gate level net list. And I expect that the output will give me the gate ordering ( port order) so I can do other computation on the code. I tried to do that using yosys command read_verilog s27.v. I was able to debug the code, yet I could not get the cell library or any thing that will get me the gate ordering.

P.S: I tried that using abc compiler and I only got the primary inputs and outputs order not the gate, and I asked before if yosys can do that and I got positive feedbacks.

module s27 ( GND, VDD, CK, R, G0, G1, G17, G2, G3 );
  input  GND, VDD, CK, R, G0, G1, G2, G3;
  output G17;
  wire   G5, G10, G6, G7, G13, n1, n2, n3, n4, n5, n6, n7, n8, n9, n11,    
         n12,n13, n14;
  DFFSR \DFF_2/Q_reg  ( .D(G13), .CLK(CK), .R(R), .Q(G7) );
  DFFSR \DFF_0/Q_reg  ( .D(G10), .CLK(CK), .R(R), .Q(G5) );
  DFFSR \DFF_1/Q_reg  ( .D(n1), .CLK(CK), .R(R), .Q(G6) );
  INVX1 U1 ( .A(G17), .Y(n1) );
  INVX1 U2 ( .A(G2), .Y(n2) );
  INVX1 U3 ( .A(G3), .Y(n3) );
  INVX1 U4 ( .A(G6), .Y(n4) );
  AND2X1 U5 ( .A(n5), .B(n2), .Y(G13) );
  AND2X1 U6 ( .A(G0), .B(G17), .Y(G10) );
  OR2X1 U7 ( .A(n6), .B(n7), .Y(G17) );
  OR2X1 U8 ( .A(n14), .B(n8), .Y(n7) );
  AND2X1 U9 ( .A(n5), .B(n9), .Y(n8) );
  OR2X1 U10 ( .A(G1), .B(n12), .Y(n5) );
  AND2X1 U11 ( .A(n3), .B(n9), .Y(n6) );
  OR2X1 U12 ( .A(G0), .B(n4), .Y(n9) );
  INVX1 U13 ( .A(G7), .Y(n11) );
  INVX1 U14 ( .A(n11), .Y(n12) );
  INVX1 U15 ( .A(G5), .Y(n13) );
  INVX1 U16 ( .A(n13), .Y(n14) );
endmodule

回答1:

The newly added torder command prints the cells in the design in topological order, if such an order exists. For example:

read_verilog test.v
hierarchy -generate * o:Y o:Q i:*
torder -stop DFFSR Q

This script applied to the code you posted produces the following output:

module s27
  cell U4
  cell U12
  cell U3
  cell U11
  cell U15
  cell U16
  cell U13
  cell U14
  cell U10
  cell U9
  cell U8
  cell U7
  cell U6
  cell DFF_0/Q_reg
  cell U1
  cell DFF_1/Q_reg
  cell U2
  cell U5
  cell DFF_2/Q_reg

Without the -stop option the command would also create dependencies for DFF output ports, which would result in loops. In such a case the command will print the loops and create a topological ordering for the remaining graph:

module s27
  loop DFF_2/Q_reg U10 U13 U14 U5
  loop DFF_0/Q_reg U15 U16 U6 U7 U8
  loop DFF_1/Q_reg U1 U11 U12 U4 U7
  cell U1
  cell DFF_1/Q_reg
  cell U4
  cell U12
  cell U3
  cell U11
  cell U15
  cell U16
  cell U2
  cell U5
  cell DFF_2/Q_reg
  cell U13
  cell U14
  cell U10
  cell U9
  cell U8
  cell U7
  cell U6
  cell DFF_0/Q_reg

I hope this helps.

来源：https://stackoverflow.com/questions/33756400/gate-level-parsing-using-yosys

标签

yosys