BCD Adder in Verilog | 易学教程

问题

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. Specifically, the adder that takes two BCD digits and adds them. So, the idea is if the sum of the two digits is less than or equal to nine, then it is correct. However, if it is greater, then an offset of 6 has to be added. Here is my Verilog code so far:

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output reg COUT,
    output reg [3:0] SUM
);

wire s2, c2;

always @ ( * ) 
begin
 assign {c2, s2} = IN_A + IN_B + CIN;

 if(s2 <= 9 && c2 == 0) begin
  assign {COUT, SUM} = {c2, s2};
 end
 else if({c2, s2} > 9) begin
  assign {COUT, SUM} = {c2, s2 + 6};
 end
end
endmodule

Anyways, when I try to synthesize it in Xilinx, I get the following errors:

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 'c2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire 's2' is not a legal reg or variable lvalue

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 Illegal left hand side of procedural assign

I tried changing some things like changing wire to reg, but I still can't get it to work. Any help is appreciated.

回答1:

Okay, I figured it out, the correct code is below. Basically, see the comment I made on my question for some tips to remember. Its funny how much simpler this is compared to the mess I had earlier.

module DIGITADD(
    input [3:0] IN_A,
    input [3:0] IN_B,
    input CIN,
    output COUT,
    output [3:0] SUM
    );

reg [4:0] s2;

assign SUM = s2[3:0];
assign COUT = s2[4];

always @ ( * )
begin
    s2 = IN_A + IN_B + CIN;
    if (s2 > 9)
    begin
        s2 = s2 + 6;
    end
end
endmodule

回答2:

In plain text, do not have a continuous assignment like "assign" statement in a procedural block i.e. always or initial.

Remember the rule and life is good :-)

来源：https://stackoverflow.com/questions/4179330/bcd-adder-in-verilog

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