How to NOT use while() loops in verilog (for synthesis)?

问题

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as:

while (num < test_number) 
     begin 
     . 
     . 
     . 
     num = num+1; 
     end

This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches. What would be the equivalent synthesizable of code of the above code segment?

Thanks!

回答1:

Synthesis tools vary but generally a loop can be synthesized so long as the number of iterations is known a to the synthesis tool. So,

for ( i = 0; i < 10; i = i + 1 )

is OK because the tool knows there are 10 loop iterations. But

reg [10:0] r;
for ( i = 0; i < r; i = i + 1 )

is not OK because r is a variable r's value is unknown at synthesis time.

Think of loops in RTL code as creating a known fixed number of copies of a piece of logic.

回答2:

You need to have a clock to control it to start.

always @(posedge clk or negedge rst_n)
  if (!rst_n)
     num <= 32'b0; // or whatever your width is.
  else
     if (num < test_number)
       num <= num + 1'b1;

回答3:

If your synthesis tool does not support while or for loops, then don't use a loop. Just expand your code out.

wire [1:0] addr;
reg  [3:0] wren;

always @(posedge clk) begin
    wren[0] <= (addr == 2'd0);
    wren[1] <= (addr == 2'd1);
    wren[2] <= (addr == 2'd2);
    wren[3] <= (addr == 2'd3);
end

I am unfamiliar with XST, but some synthesis tools do support loops (Synopsys, for example).

来源：https://stackoverflow.com/questions/2361024/how-to-not-use-while-loops-in-verilog-for-synthesis

标签

loops

verilog

synthesis