sra(shift right arithmetic) vs srl (shift right logical)

问题

Please take a look at these two pieces of pseudo-assembly code:

1)

li $t0,53

sll $t1,$t0,2
srl $t2,$t0,2
sra $t3,$t0,2

print $t1  
print $t2  
print $t3  

2)

li $t0,-53


sll $t1,$t0,2
srl $t2,$t0,2
sra $t3,$t0,2

print $t1
print $t2
print $t3

in the first case the output is:
212
13
13

in the latter is:
-212
107374...
-14
But shouldn't : sra (-53) = - (srl 53) ?

回答1:

-53 = 1111111111001011

           sra 2

      1111111111110010(11) = -14
       ^^              ^^
      sign           dropped
    extension

Because the extra bits are simply dropped for both positive and negative results, the result is always rounded down if you view the shift as a division.

 53 sra 2 = floor( 53 / 2^2) = floor( 13.25) =  13
-53 sra 2 = floor(-53 / 2^2) = floor(-13.25) = -14

回答2:

The answer relates to two's complement notation. The purpose of sra is to support negative numbers represented in two's complement. The most significant bit, which is one if the value is negative, is duplicated when shifted right in the "arithmetic" fashion.

On your 32-bit x86, this means that:

 53 = 00000000000000000000000000110101
-53 = 11111111111111111111111111001011

 srl( 53, 2) =  13 = 00000000000000000000000000001101
               -13 = 11111111111111111111111111110011

 sra(-53, 2) = -14 = 11111111111111111111111111110010

I suppose the thing to realize is that in two's complement, the negative of a number is not the inversion of every bit in the number -- it is the inversion of every bit, then the addition of 1 to that number. Consider:

 1 = 0000001
-1 = 1111111

Not:

-1 = 1111110

Which would lead to:

 0 = -1 + 1 = 11111111

In other words, there is no "negative zero" in two's complement. Zero takes up space in the realm otherwise considered "positive sign" because the high bit is zero.

来源：https://stackoverflow.com/questions/6269399/srashift-right-arithmetic-vs-srl-shift-right-logical