Video data pipelines usually consist of external devices, e.g. camera sensors,controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including video DMA engines and video data processors.
视频数据管道通常由外部设备组成，例如通过I2C、SPI或UART总线控制的摄像机传感器，以及SoC内部IP块(包括视频DMA引擎和视频数据处理器)。
SoC internal blocks are described by DT nodes, placed similarly to other SoC blocks. External devices are represented as child nodes of their respective bus controller nodes, e.g. I2C.
SoC内部块由DT节点描述，与其他SoC块放置方式类似。外部设备表示为它们各自总线控制器节点的子节点，例如I2C。
Data interfaces on all video devices are described by their child 'port' nodes. Configuration of a port depends on other devices participating in the data transfer and is described by 'endpoint' subnodes.
所有视频设备上的数据接口都由它们的子“port”节点描述。端口的配置取决于参与数据传输的其他设备，并由“endpoint”子节点描述。
device {
...
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
...
endpoint@0 { ... };
endpoint@1 { ... };
};
port@1 { ... };
};
};
If a port can be configured to work with more than one remote device on the same bus, an 'endpoint' child node must be provided for each of them. If more than one port is present in a device node or there is more than one endpoint at a port, or port node needs to be associated with a selected hardware interface, a common scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
如果一个端口可以配置为与同一总线上的多个远程设备一起工作，则必须为每个端口提供一个“endpoint”子节点。如果一个设备节点中有多个端口，或者端口上有多个端点，或者端口节点需要与选定的硬件接口相关联，则使用使用“#address-cells”、“#size-cells”和“reg”属性的常见方案。
All 'port' nodes can be grouped under optional 'ports' node, which allows to specify #address-cells, #size-cells properties independently for the 'port' and 'endpoint' nodes and any child device nodes a device might have.
所有“port”节点都可以分组再 可选的“port”节点下，该节点允许独立为“端口”和“端点”节点以及设备可能拥有的任何子设备节点指定#address-cells、#size-cells属性。
Two 'endpoint' nodes are linked with each other through their 'remote-endpoint' phandles. An endpoint subnode of a device contains all properties needed for configuration of this device for data exchange with other device. In most cases properties at the peer 'endpoint' nodes will be identical, however they might need to be different when there is any signal modifications on the bus between two devices, e.g. there are logic signal inverters on the lines.
两个“endpoint” 节点通过它们的“remote-endpoint'”相互链接。设备的端点子节点包含配置此设备所需的所有属性，以便与其他设备进行数据交换。在大多数情况下，对等“端点”节点上的属性是相同的，但是当两个设备之间总线上有任何信号修改时，它们可能需要不同，例如线路上有逻辑信号逆变器。
It is allowed for multiple endpoints at a port to be active simultaneously, where supported by a device. For example, in case where a data interface of a device is partitioned into multiple data busses, e.g. 16-bit input port divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width and data-shift properties can be used to assign physical data lines to each endpoint node (logical bus).
它允许端口上的多个端点同时处于活动状态，而设备支持这种状态。例如，当一个设备的数据接口被划分为多个数据总线时，例如16位输入端口被划分为两个单独的ITU-R BT.656 8位总线。在这种情况下，可以使用总线宽度和数据转移属性为每个端点节点(逻辑总线)分配物理数据线。
必要属性Required properties
-------------------
If there is more than one 'port' or more than one 'endpoint' node or 'reg' property is present in port and/or endpoint nodes the following properties are required in a relevant parent node:
如果存在多个“port”或多个“endpoint”节点或“reg”属性，则在相关父节点中需要以下属性:
- #address-cells : number of cells required to define port/endpoint identifier, should be 1.
- #size-cells : should be zero.
非必要属性Optional endpoint properties
----------------------------
- remote-endpoint: 远端设备节点 phandle to an 'endpoint' subnode of a remote device node.
- slave-mode: 一个布尔属性，指示链接在从属模式下运行。未指定此属性时的默认值为主模式。在从模式下，水平和垂直同步信号由主设备(数据接收器)提供给从设备(数据源)。在主模式下，数据源设备也是同步信号的源。a boolean property indicating that the link is run in slave mode.The default when this property is not specified is master mode. In the slave mode horizontal and vertical synchronization signals are provided to the slave device (data source) by the master device (data sink). In the master mode the data source device is also the source of the synchronization signals.
- bus-width: 总线位宽，适用于并行总线。number of data lines actively used, valid for the parallel busses.
- data-shift: 在并行数据总线上，如果指定了bus-width，则可以使用data-shift来指定使用哪些数据，例如。“总线带宽= < 8 >;data-shift=<2>;"表示使用了2-8位的数据。 on the parallel data busses, if bus-width is used to specify the number of data lines, data-shift can be used to specify which data lines are used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
- hsync-active: HSYNC信号的活动状态，低/高分别为0/1。 active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
- vsync-active: VSYNC信号的活动状态，低/高分别为0/1。active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
注意，如果没有指定HSYNC和VSYNC极性，可能需要在支持的情况下进行嵌入式同步。
Note, that if HSYNC and VSYNC polarities are not specified, embedded synchronization may be required, where supported.
- data-active: 指定数据行极性。 similar to HSYNC and VSYNC, specifies data line polarity.
- field-even-active: 场信号电平均匀时场数据传输。 field signal level during the even field data transmission.
- pclk-sample: 采样数据上的上升(1)或下降(0)边缘的像素时钟信号。 sample data on rising (1) or falling (0) edge of the pixel clock signal.
- sync-on-green-active: 同步绿色(SoG)信号的激活状态，低/高分别为0/1。 active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively.
- data-lanes: 在mipi总线下，数据lane的指定。an array of physical data lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0. This property is valid for serial busses only (e.g. MIPI CSI-2).
- clock-lanes: 在mipi总线下，时钟lane的指定。an array of physical clock lane indexes. Position of an entry determines the logical lane number, while the value of an entry indicates physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the clock lane on hardware lane 0. This property is valid for serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this array contains only one entry.
- clock-noncontinuous: 允许MIPI CSI-2非连续时钟模式的布尔属性。a boolean property to allow MIPI CSI-2 non-continuous clock mode.
- link-frequencies: 允许数据总线频率。例如，对于MIPI CSI-2，这是总线的实际频率，而不是每个时钟每个车道值的位。一个64位无符号整数数组。Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the actual frequency of the bus, not bits per clock per lane value. An array of 64-bit unsigned integers.
- lane-polarities: 从时钟通道开始，然后按与数据通道相同的顺序跟随数据通道的极性数组。有效值为0(正常)和1(倒置)。数组的长度应该是数据通道和时钟通道属性的组合长度。如果省略了lane- pol属性，则该值必须解释为0 (normal)。此属性仅对串行总线有效。an array of polarities of the lanes starting from the clock lane and followed by the data lanes in the same order as in data-lanes. Valid values are 0 (normal) and 1 (inverted). The length of the array should be the combined length of data-lanes and clock-lanes properties.If the lane-polarities property is omitted, the value must be interpreted as 0 (normal). This property is valid for serial busses only.
来源：https://blog.csdn.net/dragon101788/article/details/99445027