Is rising_edge in VHDL synthesizable

问题

In my coding when I write this statement, it is simulated, but not synthesizable. why? Now what should I do to solve this problem???

IF ((DS0='1' OR DS1='1')and rising_edge(DS0) and rising_edge(DS1) AND DTACK='1' AND BERR='1') THEN
RV0 <= not RV;
else
RV0 <= RV;

回答1:

The most important thing when doing FPGA-designs is to think hardware.

An FPGA consists of a number of hardware blocks, with a predetermined set of inputs and outputs - the code you write needs to be able to map to these blocks. So even if you write code that is syntactically correct, it doesn't mean that it can actually map to the hardware at hand.

What your code tries to do is:

IF ((DS0='1' OR DS1='1')and rising_edge(DS0) and rising_edge(DS1) AND DTACK='1' AND BERR='1') THEN
(...)

If DS0 and DS1 currently have a rising edge (implying that they're also both '1', making the first part with (DS='1' OR DS1='1') redundant), and if DTACK and BERR are both 1, then do something.

This requires an input block that takes two clock inputs (since you have two signals that you want to test for rising edges simultaneously), and such a block does not exist in any FPGA I've encountered - and also, how close together would such two clock events need to be to be considered "simultaneous"? It doesn't really make sense, unless you specify it within some interval, for instance by using a real clock signal (in the sense of the clock signal going to the clock input of a flip-flop), to sample DS0 and DS1 as shown in Morten Zilmers answer.

In general, you'd want to use one dedicated clock signal in your design (and then use clock enables for parts that need to run slower), or implement some cross-clock-domain synchronization if you need to have different parts of your design run with different clocks.

Depending on the IDE environment you use, you may have access to some language templates for designing various blocks, that can help you with correctly describing the available hardware blocks. In Xilinx ISE you can find these in Edit > Language Templates, then, for instance, have a look at VHDL > Synthesis Constructs > Coding Examples > Flip Flops.

回答2:

An addition to sonicwave's good answer about thinking hardware and synthesis to the available elements.

The rising_edge function is generally used to detect the rising edge of a signal, and synthesis will generally use that signal as a clock input to a flip-flop or synchronous RAM.

If what you want, is to detect when both DS0 and DS1 goes from '0' to '1' at the "same" time, then such check is usually made at each rising edge of a clock, and the change is detected by keeping the value from the previous rising clock.

Code may look like:

...
  signal CLOCK    : std_logic;
  signal DS0_PREV : std_logic;
  signal DS1_PREV : std_logic;
begin
  process (CLOCK) is
  begin
    if rising_edge(CLOCK) then
      if (DS0 = '1' and DS0_PREV = '0') and  -- '0' to '1' change of DS0
        (DS1 = '1' and DS1_PREV = '0') and   -- '0' to '1' change of DS1
        DTACK = '1' AND BERR = '1' then
        RV0 <= not RV;
      else
        RV0 <= RV;
      end if;
      DS0_PREV <= DS0;  -- Save value
      DS1_PREV <= DS1;  -- Save value
    end if;
  end process;
...

来源：https://stackoverflow.com/questions/26795774/is-rising-edge-in-vhdl-synthesizable

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