问题
We know that we can get AST textfile of Verilog code. Now I want to modify the AST to get some new features, Is ANTLR right for this job,or which software should I use? Or How should I do? Then, I want to synthesis the modified AST to generate Verilog code? Can YOSYS finish this Job? What should I do? Can you tell me in detail？ Thanks for your help!
回答1:
ANTLR parses, but is not particularly good at supporting modifications to the AST or regenerating the source code accurately.
Our DMS Software Reengineeringing is designed to do these tasks. See our Verilong Front End for round-trip parsing and un-parsing, and DMS's support for modifying ASTs using source-to-source transformations.
回答2:
With ANTLR 4 for AST transforming you can use generated class Visitor by overriding Visit methods. All Visit methods should return AST node of your target type.
来源：https://stackoverflow.com/questions/37409964/how-to-modify-an-ast-from-yosys-and-how-to-synthesis-a-modified-ast-to-verilog