问题
Assuming 2 gate-delays for a Sum or Carry function, estimate the time for ripple-through carry addition for adders with the following word lengths:-
i) 4-bit
ii) 8-bit
iii) 16-bit
In my notes I have written: "delay is the word width times each bit stage delay (2 gate delays)". Therefore:
i) 2*4 = 8
ii) 2*8 = 16
iii) 2*16 = 32
Looking at the ripple carry adder wikipedia page: http://en.wikipedia.org/wiki/Ripple_carry_adder#Ripple-carry_adder
The formula used here is different, can anyone explain the discrepancy between my notes and the wikipedia article. Which of the two is correct?
Thanking you in advance.
Joe
回答1:
As you can see from the figure in the linked wikipedia article, your assumption is a simplification:
The critical path for C_out contains three gates, i.e. delays. However, you need the three delays only for the first stage, since for the following only C_in changes, what leads to a critical path of only two gates for the second and all following stages.
来源：https://stackoverflow.com/questions/16376607/boolean-logic-gate-delays