Binary coded decimals in verilog

问题

I wrote the following code for BCD to seven segment. The code compiles find and simulates too but the value of num is not going beyond 2. I don't know why is that. Here is the code:

module BCDtoSeven_TOP
  reg  [3:0] num;
  wire a,b,c,d,e,f,g;

  BCDtoSeven s(num,a,b,c,d,e,f,g);

  initial begin
    num=1;
  end

  always @(num<=9) begin
    #2 num=num+1;
  end

endmodule

Sub Module:

module BCDtoSeven(num,a,b,c,d,e,f,g);

  output a,b,c,d,e,f,g;
  input  [3:0] num;

  assign a=(num==4 || num==5 || num==6 || num==7 || num==8 || num==9)? 1:0;
  assign b=(num==2 || num==3 || num==5 || num==6 || num==7 || num==8 || num==9)? 1:0;
  assign c=(num==2 || num==3 || num==8 || num==9 || num==7)? 1:0;
  assign d=(num==4 || num==3 || num==5 || num==8 || num==9 || num==7)? 1:0;
  assign e=(num==5 || num==3 || num==6 || num==8 || num==9)? 1:0;
  assign f=(num==2 || num==1 || num==6 || num==8 )? 1:0;
  assign g=(num==2 || num==3 || num==6 || num==8 || num==9 || num==5 )? 1:0;
endmodule

回答1:

The always @ block gets executed any time a signal in its sensitivity list changes. num<=9 remains true so the block only executes once.

An alternative using a clock might look like:

always @(posedge clk) begin
    if(num <= 9) begin
        num = num+1;
    end
end

来源：https://stackoverflow.com/questions/14323107/binary-coded-decimals-in-verilog