问题
I am using SystemC for modelling, and I am a little bit confused about the "channel", which includes signal, buffer and fifo.
So could anyone tell me the difference of signal and buffer? Is it the same as the difference between the wire and register variable in Verilog HDL? Can signal be bound to the buffer variable?
回答1:
sc_buffer and sc_signal are both primitive channels that implement sc_signal_inout_if; a 'buffer' is an object of type sc_buffer, while a 'signal' is an object of type sc_signal. The only difference between the two is that you get a value-change event whenever a buffer is written, whether or not it changes value.
There's no equivalent in Verilog, so nothing to do with wires and registers. There is something similar in VHDL. <sig>'transaction gives you an implicit signal which toggles between '0' and '1' in a delta cycle whenever <sig> is written to, irrespective of whether or not <sig> changes. <sig>'event is only true in a delta when <sig> has actually changed.
So, in short, use a buffer when you need to know if a channel has been written to, even if the write didn't change anything.
来源：https://stackoverflow.com/questions/18824286/in-systemc-can-the-sc-signal-in-out-type-port-be-bound-to-the-primary-channel-s