问题
I try to dump an array (reg [31:0] data [31:0]) but I can't do it successfully. I've tried the way that is in the iverilog wiki:
integer idx;
for (idx = 0; idx < 32; idx = idx + 1)
$dumpvars(0,cpu_tb.cpu0.cpu_dp.cpu_regs.data[idx]);
It works, but 2 things happen.
- A warning shows up: VCD warning: array word cpu_tb.cpu0.cpu_dp.cpu_regs.data[0] will conflict with an escaped identifier.
- In GTKWave I have something like this in SST window: \data[0][31:0]
Is there any solution about that?
Thanks in advance and sorry for my English.
回答1:
I have e-mailed the mailing list of Icarus Verilog. Here are some answers:
To dump an array word Icarus needs to escape the name so it is compatible with the VCD dump format. That's what \data[0][31:0] is. It is the zeroth 32-bit word of the data array. Because an escaped name and an array name could now conflict Icarus produces the warning. It would be best if it could check for an escaped identifier conflict and only print a message when there is a problem, but as I remember this was not possible.
We chose to use escaped identifiers so that all the dumpers could handle array words. The other common choice is to only support them using a special dump command that only works with certain dump formats.
I agree it would be nice if we could make the warning more accurate, but we are usually busy working on other things so minor annoyances that appear to be complicated to fix do not often get fixed. As I remember, and it has been a number of years, the issue is if you search for the escaped identifier it find the array element and there is no way in the VPI to search for the next occurrence. It's possible that finding the array element in the Icarus search by name implementation is a bug.
Cary
"To dump an array word Icarus needs to escape the name so it is compatible with the VCD dump format. That's what \data[0][31:0] is. It is the zeroth? 32-bit word of the data array. Because an escaped name and an array name could now conflict Icarus produces the warning. It would be best if it could check for an escaped identifier conflict and only print a message when there is a problem, but as I remember this was not possible."
...I don't think that there's a need to escape the names. Both VCS (followed by fsdb2vcd) and CVC emit the name directly with no problems. Cut and paste example shown below:
$var wire 5 `' IC_DrAd0 [3][4:0] $end $var wire 5 a' IC_DrAd0 [2][4:0] $end $var wire 5 b' IC_DrAd0 [1][4:0] $end $var wire 5 c' IC_DrAd0 [0][4:0] $end
I realize the VCD spec doesn't define this, but I've had to fold in a lot of these kinds of extensions into gtkwave over the years as other tools generate these constructs. The escapes can cause save file incompatibilities (missing signals) when trying to simulate on iverilog versus VCS.
Over time, SV constructs likely will cause further things added to the VCD files. AFAIK, the VCD part of the 1364 spec hasn't updated at all since Verilog-XL. CVC gets around possible incompatibilities by adding a +dump_arrays plusarg (and no, you don't have to loop on each array element either).
-Tony
I also sent a mail to GTKWave creator Tony Bybell:
Hello,
The problem is that the compiler is not emitting those values into the dump file. You'll have to get in contact with the iverilog developers. I see the same problem if I run sim and compare against another simulator such as CVC with +dump_arrays turned on which does dump the arrays and they are visible in gtkwave.
http://iverilog.wikia.com/wiki/Release_Notes_Icarus_Verilog_0_9_2 | Allow $dumpvars to accept array members for dumping,
...it looks like during "initial" time you might need to add a $dumpvars statement for each array element you want dumped. I don't know if the array name by itself works. Assigning each element to a "wire" might work too.
I have never tried this functionality in iverilog so I don't know if it works. You might have to experiment or ask the developers.
-Tony
来源：https://stackoverflow.com/questions/20317820/icarus-verilog-dump-memory-array-dumpvars