问题
The aim of my project is to load 3 bitstreams into the PROM; according to our requirement we load the 1or second or 3 bit file.
The way i approached to the problem statement is :
- Initially I have taken 2 trigger inputs, depending on it the 2 or 3 bit file will be loaded.. as the default one would be the First bit file (User Logic).
USER LOGIC : Explanation
First I have instantiated the ICAP Virtex 6 primitive, secondly, I have written a State machine in which I'm sending few IPROGRAM command sequence.
The IPROGRAM Command sequence consists of Warm Boot starting address and I have given the Address of the 2nd Bit file and also 3rd . and loading it.
My problem is, the state machine is working but the 2nd Bit or 3 bit file is not being loaded...I'm not sure even the ICAP is searching the PROM for the 2nd bitstream.....I have seen the example design files provided by the xilinx..but it was of no help
Here, I'm adding the code which I have coded.. Thank you
module test_1(
I0,
I1,
TRIGGER,
status,
A
);
input I0;
input I1;
input TRIGGER;
output reg [7:0] status;
output reg [3:0] A;
wire clk;
parameter[3:0] STATE_00 = 0;
parameter[3:0] STATE_01 = 1;
parameter[3:0] STATE_02 = 2;
parameter[3:0] STATE_03 = 3;
parameter[3:0] STATE_04 = 4;
parameter[3:0] STATE_05 = 5;
parameter[3:0] STATE_06 = 6;
parameter[3:0] STATE_07 = 7;
parameter[3:0] STATE_08 = 8;
parameter[3:0] STATE_09 = 9;
parameter[3:0] STATE_10 = 10;
parameter[3:0] STATE_11 = 11;
reg[3:0] NEXT_STATE = STATE_03;// STATE_00;
reg CE = 1'b1;
reg[31:0] I = 32'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;;
reg ICAP_WRITE = 1'b1;
reg [1:0] counter;
reg clock_2mhz_out;
reg switch=1'b0;
// //---------Differential Clock---------------------------------------------
// BUFGMUX: Global Clock Mux Buffer
// Virtex-6
// Xilinx HDL Language Template, version 14.4
IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
) IBUFGDS_inst (
.O(clk), // Clock buffer output
.I(I0), // Diff_p clock buffer input
.IB(I1) // Diff_n clock buffer input
);
//--------------------------------------------------------------------------
//----------------ICAP PRIMITIVE--------------------------------------------
// ICAP_VIRTEX6: Internal Configuration Access Port
// Virtex-6
// Xilinx HDL Language Template, version 14.4
ICAP_VIRTEX6 #(
.DEVICE_ID(32'h04244093), // Specifies the pre-programmed Device ID value
.ICAP_WIDTH("X32"), // Specifies the input and output data width to be used with the
// ICAP_VIRTEX6.
.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
// model
)
ICAP_VIRTEX6_inst (
.BUSY(), // 1-bit output: Busy/Ready output
.O(), // 32-bit output: Configuration data output bus
.CLK(clk), // 1-bit input: Clock Input
.CSB(CE), // 1-bit input: Active-Low ICAP input Enable
.I(I), // 32-bit input: Configuration data input bus
.RDWRB(ICAP_WRITE) // as of now the write operation is 0
// 1-bit input: Read/Write Select input
);
// End of ICAP_VIRTEX6_inst instantiation
always@(negedge clk)
begin
if(TRIGGER == 1'b1)
begin
switch<=1'b1;
end
end
always@(negedge clk)
begin
if(switch == 1'b1)
begin
case(NEXT_STATE)
STATE_03:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'h4;
I <= 32'hFFFFFFFF;
NEXT_STATE <= STATE_04;
end
STATE_04:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'h5;
I <= 32'h5599AA66;
NEXT_STATE <= STATE_05;
end
STATE_05:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'h6;
I <= 32'h0400_0000;
NEXT_STATE <= STATE_06;
end
STATE_06:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'h7;
I <= 32'h0C40_0080;
NEXT_STATE <= STATE_07;
end
THE SECONF BIT FILE IS NOT BEING ADDED...SO THE OUTPUT IS NOT COMING...
THE SECONG BIT FILE CONSISTS OF A 1'BIT LED...WHICH I CONNECTED IT TO A GPIO
STATE_07:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'hff;
I <= 32'h3062CE59; The address i got when I'm lOADING THE pROM FILE
A <= 4'b1010;
NEXT_STATE <= STATE_08;
end
STATE_08:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'h9;
I <= 32'h0C00_0180;
NEXT_STATE <= STATE_09;
end
STATE_09:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'hA;
I <= 32'h000000F0;
NEXT_STATE <= STATE_10;
end
STATE_10:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b0;
status <= 8'hB;
I <= 32'h04000000;
NEXT_STATE <=STATE_00 ;
end
STATE_11:
begin
ICAP_WRITE <= 1'b0;
CE <= 1'b1;
status <= 8'hC;
I <= 32'h00000000;
NEXT_STATE <= STATE_11;
end
default:
begin
ICAP_WRITE <= 1'b1;
CE <= 1'b1;
status <= 8'hD;
I <= 32'hAAAAAAAA;
NEXT_STATE <= STATE_00;
end
endcase
end
end
else
begin
ICAP_WRITE <= 1'b1;
CE <= 1'b1;
status <= 8'hE;
I <= 32'hAAAABBBB;
NEXT_STATE <= STATE_00;
end
end
endmodule
来源：https://stackoverflow.com/questions/27153614/reconfiguration-of-fpga-in-ml605-board