问题
I am trying to learn VHDL and struggling with some of its basics. The question is as follows:
Process statement is described to contain code that runs sequentially (one line after the other). I want to ask why can't one run concurrent code in a process statement (means all lines execute in parallel). Secondly, if process statement contains sequential code, how can it model for example, three flip-flops concurrently e.g.,
--inside process statement
Q1 <= D1;
Q2 <= Q1;
Q3 <= Q2;
回答1:
Sequential relates to the order the statements are evaluated, not when the assignment takes effect.
The VHDL Simulation Cycle
Signal assignments don't take effect immediately, they are scheduled for the current or a future time and all processes sensitive to signal transactions in the current simulation cycle being are completed before the assignments take effect. (And in VHDL everything devolves into equivalent block hierarchy, processes and function calls for simulation.)
When all currently active processes complete simulation time advances to the next time a signal is active in any signal projected output waveform (a queue) unless there are events at the current simulation time, in which case we call the next simulation cycle a delta cycle.
Each process that is sensitive to a signal's transactions is executed and any further signal assignments are made to the respective projected output waveform. There is only one 'slot' in the queue for the current simulation time for each signal.
In this way there aren't any processes hitting moving targets. Only one process executes at a time, no signal assignments take effect until all processes have completed execution. This emulates concurrency, mimicking parallel execution when processes containing sequential statements are executed sequentially.
An assignment such as Q1 <= D1; is equivalent to Q1 <= D1 after 0 ns; meaning the current simulation time. If a series of sequential statements in a process contain a subsequent assignment to the same signal at the current simulation time and the assigned value is different the second assignment will replaced the first one in the projected output waveform.
When there are no more events scheduled for signals at the current simulation time, simulation time will advance to the earliest time of any transaction time in any projected output waveform queue advancing simulation time.
When there are no further queue events simulation time will advance to Time'HIGH (the highest possible simulation time) and simulation will cease.
Also simulation can be stopped by an implementation controlling how long to allow the simulation to run or by execution of an assertion statement with a SEVERITY LEVEL of FAILURE or an implementation defined severity level threshold for stopping simulation.
来源：https://stackoverflow.com/questions/23664124/process-statement-in-vhdl