How to to create include files in vhdl?

Question

I need to use one module, I created previously using vhdl in another module and I cant find any info on how to do this. I'm forced to use maxplus2, and the only thing I found there is that I can create include file there (will have .inc extension), but I still cant get it included in my second module. I've spent the whole morning searching for this info but found nothing. Can anybody help me with it?

Answer 1

You don't.

VHDL doesn't have include files, it avoids that whole horrid disastrous unreliable mess.

VHDL uses separate compilation, and good VHDL tools (not all of them!) track all the dependencies correctly without includes or Makefiles.

So you compile your other modules into a library - maybe "my_modules" - or if you don't specify a library, just compile it, it'll go into the default library called "work".

Then in your main module you name the libraries (except "work" which is always there)

library ieee;
library my_modules;

and name the things (modules, packages) you want from them (except "work" ...)

use ieee.numeric_std.all;
use my_modules.all;

and you can now use whatever you want from these libraries. The simplest way to use a module is "direct entity instantiation" - searching this and "VHDL" will show you how. Or you can declare a component in your main module with the same ports as your other module, and the correct module will replace the component at elaboration (VHDL term for linking). Where you would need a component is if you haven't written the library modules yet - i.e. top down design... otherwise direct entity instantiation is simpler.

For now, ignore "my_modules" and just use "work" - when you get to a big design, use libraries to organise it, e.g. keep hardware and testbenches separate.

Answer 2

Brian has the right answer for you. Something I'd add which is related to your question in that it's something else people use include files for:

packages are VHDL's way of sharing data-types, constants, functions and procedures.