How to shift a std_logic_vector by std_logic_vector using concatenation

问题

Say I have 2 std_logic_vectors:

inputA : std_logic_vector(31 downto 0)
inputB:  std_logic_vector(31 downto 0)

How do I shift inputA by inputB using concatenation?

I know how to shift left or right by 1 place but can't figure out how to shift N places to the right (or left). Note: this is a clockless circuit, and can't use standard vhdl shift operators.

Other techniques or ideas other than concatenation would be appreciated as well.

回答1:

I prefer wjl's approach, but given you asked specifically for a method using concatenation, try this:

function variable_shift(i : std_logic_vector, num_bits : integer) 
   return std_logic_vector is
   constant zeros : std_logic_vector(num_bits-1 downto 0) := (others => '0');
begin
   return i(i'high-num_bits downto i'low) & zeros;
end function;

(It could be written to take a second std_logic_vector for the num_bits parameter, but as it's fundamentally a number, I'd always use a number-based type for it)

回答2:

The simplest way to do this would be to something like this:

library ieee;
use ieee.numeric_std.all;
...
output <= std_logic_vector(unsigned(inputA) srl to_integer(unsigned(inputB)));

(BTW, being a clockless circuit has nothing to do with being able to use shift operators or not. What determines that is data types. This shift operation will be turned into the same logic by a synthesizer as you would get if you wrote something more complex with case statements all expanded out by hand.)

来源：https://stackoverflow.com/questions/12447010/how-to-shift-a-std-logic-vector-by-std-logic-vector-using-concatenation