What does |variable mean in verilog?

问题

I am wondering what assign hd_trs_detected = |hd_trs_match; means in verilog. I am mostly interested in the |hd_trs_match part. I know that | means bit wise OR, but not sure how to interpret it without a value before the |. Is it an understood '1' or '0'? If it is a '0', what would be the advantage of using |hd_trs_match vs. just hd_trs_match as hd_trs_detected would always be whatever hd_trs_match is? Or could it be a bit wise operation of itself.

回答1:

In this ussage the | is a reduction operator, not a bit-wise operator. Reduction operator are described in the Reduction operators section all version of the LRM. From Verilog's original IEEE Std 1364-1995 in § 4.1.11 to the latest SystemVerilog IEEE Std 1800-2012 in § 11.4.9. Here is an excerpt from IEEE Std 1800-2012 § 11.4.9:

The unary reduction operators shall perform a bit-wise operation on a single operand to produce a single-bit result. For reduction AND, reduction OR, and reduction XOR operators, the first step of the operation shall apply the operator between the first bit of the operand and the second using Table 11-16 through Table 11-18. The second and subsequent steps shall apply the operator between the 1-bit result of the prior step and the next bit of the operand using the same logic table. ...

Bit-wise and reduction operators use the same character (ex: |, &, ^). To distinguish the two, check of a value on the left side of the operator. If there is an value, then it is bit-wise, if nothing, then reduction.

You could mix bit-wise and reduction in the same expression. For example out = &in1 ^ |in2; where the & and | are reduction operator (no values on their lefts) and the ^ is bit-wise ( the result of &in1 is the left value). However, to be more human readable, it is recommenced to make the reduction operations more visually explicit with parenthesizes: out = (&in1) ^ (|in2);

回答2:

The | is a reduction operator. For a multi-bit signal, it produces an output applying the operand to each bit of the vector.

For example,

wire [3:0] in;
wire out;
assign out = |in; // the same as out = in[3] | in[2] | in[1] | in[0];

You can do the same with &, ^, etc.

来源：https://stackoverflow.com/questions/38576677/what-does-variable-mean-in-verilog