问题
With the standard 5-stage pipeline for the MIPS architecture and assuming some instructions depend on each other, how the pipeline bubbles are inserted to the following assembly code?
I1: lw $1, 0($0)
I2: lw $2, 4($0)
I3: add $3, $1, $2 ; I1 & I2 -> I3
I4: sw $3, 12($0) ; I3 -> I4
I5: lw $4, 8($0)
I6: add $5, $1, $4 ; I1 & I5 -> I6
I7: sw $5, 16($0) ; I6 -> I7
In the first place that we insert a bubble, we
I1: IF ID EX MEM WB
I2: IF ID EX MEM
I3: IF ID --
I4: IF ID
As you can see, while I3 is stalled, I4 can proceed for decoding. Isn't that right? Next,
I1: IF ID EX MEM WB
I2: IF ID EX MEM WB
I3: IF ID -- EX MEM WB
I4: IF ID -- -- EX MEM WB
I5: IF ID EX MEM WB
I6: IF ID -- EX MEM WB
I7: IF ID -- -- EX MEM WB
I think that is possible with the standard pipeline of MIPS, but some say that whenever a bubble is inserted the whole pipeline is stalled. How that can be figured out?
回答1:
In your previous question you were using Patterson's book, so let me borrow one of its diagrams:
The important bit here is the hazard detection unit, which is causing the bubbles. If you've read the accompanying text, you know that the method by which it does that is
- NOP out the control signals,
- pause IF (keep the IF/ID buffer fixed and don't advance PC)
Which means that your pipeline diagram cannot happen like that. There will not be a new instruction entering every cycle. Also consider that if you had different code, you could have arranged for hardware hazards to happen, as Jester described. So that's obviously bad, and the solution is stalling IF.
This is what would happen:
I1: IF ID EX MEM WB
I2: IF ID EX MEM WB
I3: IF ID -- -- --
I3: IF ID -- -- --
I3: IF ID EX MEM WB
I4: IF ID -- -- --
etc.
来源：https://stackoverflow.com/questions/33941907/understanding-mips-assembly-with-pipelining