zero-extension

x86_64 registers rax/eax/ax/al overwriting full register contents [duplicate]

牧云@^-^@ 提交于 2019-11-26 23:42:52
This question already has an answer here: Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register? 2 answers As it is widely advertised, modern x86_64 processors have 64-bit registers that can be used in backward-compatible fashion as 32-bit registers, 16-bit registers and even 8-bit registers, for example: 0x1122334455667788 ================ rax (64 bits) ======== eax (32 bits) ==== ax (16 bits) == ah (8 bits) == al (8 bits) Such a scheme may be taken literally, i.e. one can always access only the part of the register using a designated name for reading

x86_64 registers rax/eax/ax/al overwriting full register contents [duplicate]

时间秒杀一切 提交于 2019-11-26 08:48:19
问题 This question already has an answer here: Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register? 2 answers As it is widely advertised, modern x86_64 processors have 64-bit registers that can be used in backward-compatible fashion as 32-bit registers, 16-bit registers and even 8-bit registers, for example: 0x1122334455667788 ================ rax (64 bits) ======== eax (32 bits) ==== ax (16 bits) == ah (8 bits) == al (8 bits) Such a scheme may be taken

Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?

混江龙づ霸主 提交于 2019-11-25 21:44:08
问题 In the x86-64 Tour of Intel Manuals, I read Perhaps the most surprising fact is that an instruction such as MOV EAX, EBX automatically zeroes upper 32 bits of RAX register. The Intel documentation (3.4.1.1 General-Purpose Registers in 64-Bit Mode in manual Basic Architecture) quoted at the same source tells us: 64-bit operands generate a 64-bit result in the destination general-purpose register. 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination