VJTAG转VME DTB
/* VME : DTB Modules Master Sim */ module vme_sim ( input clk,//40mHz input rst_n, //-------------------------- output reg [5:0]am, output reg as_n, output reg ds0_n, output reg ds1_n, output reg lword_n, output reg write_n, output reg [23:1] addr, inout [15:0] data, //-------------------------- input dtack_n //--------------------------- ); reg data_en;/*synthesis preserve = 1*/ reg[15:0] data_o;/*synthesis preserve = 1*/ reg [15:0] vme_data;/*synthesis preserve = 1*/ reg vme_ack;/*synthesis preserve = 1*///下降沿说明要读的数据已经完成 wire [31:0] mv_regs[3:0];/*synthesis preserve = 1*/ wire udr;/