transactional-memory

问题 I'm confused because from reading the wiki page it seems like just having a checkValidate and commit system for loads and stores. Is the purpose to solve synchronization problems? Is it a software programming thing build on-top of current hardware, or is it a hardware implementation via an ISA? What's the difference between each (HW/SW) implementation? Thanks. 回答1: Transactional Memory is the concept of using transactions rather than locks to synchronise processes that execute in parallel and

问题 I'm confused because from reading the wiki page it seems like just having a checkValidate and commit system for loads and stores. Is the purpose to solve synchronization problems? Is it a software programming thing build on-top of current hardware, or is it a hardware implementation via an ISA? What's the difference between each (HW/SW) implementation? Thanks. 回答1: Transactional Memory is the concept of using transactions rather than locks to synchronise processes that execute in parallel and

问题 I'm confused because from reading the wiki page it seems like just having a checkValidate and commit system for loads and stores. Is the purpose to solve synchronization problems? Is it a software programming thing build on-top of current hardware, or is it a hardware implementation via an ISA? What's the difference between each (HW/SW) implementation? Thanks. 回答1: Transactional Memory is the concept of using transactions rather than locks to synchronise processes that execute in parallel and

问题 From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever. But when a transaction aborts, it would be good to see what address - or cache line - caused it (when such a thing was the reason for the abort). Is the address exposed anywhere? 回答1: After talking to folks at Intel, there is no way to do this [citation]. The address is

问题 From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever. But when a transaction aborts, it would be good to see what address - or cache line - caused it (when such a thing was the reason for the abort). Is the address exposed anywhere? 回答1: After talking to folks at Intel, there is no way to do this [citation]. The address is

问题 it is possible using TSX-Transactional Synchronization Extensions with WebAssembly? I didn't find anything about using those extensions in WebAssembly. thanks! 回答1: Nope that is impossible. This is i386 specific extension. So it is only possible to use it in actual WebAssembly implementation but not with WebAssembly moduls or any code targeting WebAssembly. 来源： https://stackoverflow.com/questions/59201721/using-tsx-with-webassembly

问题 What is the transactional memory in comparison to actor-based and lock-based synchronization? As far as I understand it is another mechanism of concurrency control. Or it is something completely different to actors, events, locks etc.? 回答1: Transactional Memory (TM) is a lock free synchronization methodology. In a lock based synchronization mechanism, one thread acquires the lock and enters the synchronized block whilst others wait until the lock becomes available. In TM, threads don't wait

问题 What is the current status of transactional memory proposal for C++17. Is it going to be included in the standard, aimed at being included in some future version of standard C++ or is only an experimental proof-of-concept feature, with its standardization status still undetermined? I'm asking because some of the standardization committee's documents seem to give contradictory communication here. On the one hand we have P0265R0 (http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0265r0

问题 Is enough just to declare all of the functions as transaction_safe in some my class, so its can be used as thread-safe in transactions atomic_noexcept, atomic_cancel, atomic_commit from Experimental Transactional Memory TS? As known there are Transactional Memory TS (ISO/IEC TS 19841:2015) in the Experimental C++ standard libraries. Simple examples are here: http://en.cppreference.com/w/cpp/language/transactional_memory Also there is Technical Specification for C++ Extensions for

问题 Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX). As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly) Then, Can I track transactional memory operations and get information like address, and values of read/write-set? 回答1: You cannot. There is no (public) interface to the HTM hardware buffers. 回答2: Read-Set and Write-Set are