spartan

serial monitoring method to test communication via com ports without a serial communication device

由 ╄→гoц情女王★ 提交于 2021-01-29 07:46:42
问题 I have a Verilog code simulated and synthesized on ISE design toolkit. I've got an FPGA spartan 6 device which is to be used for the implementation. But there is a problem with the device (probably a power issue) which makes the device unavailable in any of the COM ports when I connected it to my PC. So I want to check whether my Matlab code which I made for serial communication through the device does the desired job. So I need a method to test serial communication via any of the COM ports

FIFO implementation - VHDL

由 Deadly 提交于 2019-12-14 00:11:56
问题 I come across one more difficulty while instantiate the fifo code to my top module. I want to store some set of data say "WELCOME TO THE WORLD OF FPGA" from my serial port ( receiving subsystem) then i want to retrieve it back say when button on fpga board is pressed or FIFO is full. I have my fifo code and serial communication code written. Idea is data sent from keyboard ->receiving subsystem -> FIFO -> transmitting subsystem -> hyperterminal. I am at present using fifo of 8 bit wide and

Counter with push button switch design using VHDL and Xilinx

由 那年仲夏 提交于 2019-12-13 04:14:49
问题 I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a very simple counter with the following inputs: Direction Count The count input will be assigned to a button and I want the counter to count up or down according to direction input when the button is pressed. I have written a sample VHDL before this one. It had a clock input and It was counting according to the clock input. Now I want it to count when I press the button instead of counting

VHDL - connect switch and LED

由 限于喜欢 提交于 2019-12-11 15:47:38
问题 I have the Xilinx Spartan6 and next VHDL code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Switches_Leds is Port (switch_0: in STD_LOGIC; LED_0 : out STD_LOGIC); end Switches_Leds; architecture Behavioral of Switches_Leds is begin LED_0 <= switch_0; end; Here is my User constraint file: NET "switch_0" LOC = C3; NET "LED_0" LOC = P4; My question is: Why the led is always is turned on, but it goes off if I click on button ? I explain: I program my fpga - the led

Verilog Tri-State Issue (Xilinx Spartan 6)

由 自古美人都是妖i 提交于 2019-12-11 09:08:29
问题 Referring to my earlier question here, I've been utilizing tri-states to work with a common bus. I still appear to have some implementation issues. The tri-states use this type of code: assign io [width-1:0] = (re)?rd_out [width-1:0]:{width{1'bz}}; Synthesis and translation goes well. No warnings or errors I wasn't expecting (I was expecting some since this is only a trial run and most of the components don't do anything and will hence be left unconnected). But when I actually try to

Using BUFG to drive clock loads

由 社会主义新天地 提交于 2019-12-10 11:03:51
问题 I'm attempting to work with pixel data that is output to a DVI chip. A variety of clock frequencies are used because the DVI chip registers are programmed using I2C (therefore needs a clock < 500 KHz) - from a clock divider. The DVI chip needs a 40 MHz differential pixel clock, however, the DVI takes displays half a byte twice a cycle, so a further 80 MHz clock is needed to push each half of the pixel onto the data lines with each half cycle, these are from a DCM. This has led to a variety of

Using BUFG to drive clock loads

由 时光总嘲笑我的痴心妄想 提交于 2019-12-06 08:23:41
I'm attempting to work with pixel data that is output to a DVI chip. A variety of clock frequencies are used because the DVI chip registers are programmed using I2C (therefore needs a clock < 500 KHz) - from a clock divider. The DVI chip needs a 40 MHz differential pixel clock, however, the DVI takes displays half a byte twice a cycle, so a further 80 MHz clock is needed to push each half of the pixel onto the data lines with each half cycle, these are from a DCM. This has led to a variety of problems. I attempted to just use the double pixel clock rate to swap each half of the pixel, however

How to count pressed keys on FPGA spartan board

由 ▼魔方 西西 提交于 2019-11-27 16:23:51
I`m using FPGA Spartan 2 board and want to count the keys pressed from Keyboard this is my VHDL code : library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; ENTITY Keyboard IS PORT(CLOCK : IN STD_LOGIC; RESET : IN STD_LOGIC; RK : IN STD_LOGIC_VECTOR(3 DOWNTO 1); DE : OUT STD_LOGIC_VECTOR(3 DOWNTO 1); Invalid_Key : OUT STD_LOGIC := '0'; Seg1 : OUT STD_LOGIC_VECTOR(7 Downto 0); Seg2 : OUT STD_LOGIC_VECTOR(7 Downto 0); LEDRow1 : OUT STD_LOGIC_VECTOR(7 Downto 0); LEDRow2 : OUT STD_LOGIC_VECTOR(7 Downto 0); Key : OUT STD

How to count pressed keys on FPGA spartan board

由 眉间皱痕 提交于 2019-11-26 18:38:54
问题 I`m using FPGA Spartan 2 board and want to count the keys pressed from Keyboard this is my VHDL code : library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; ENTITY Keyboard IS PORT(CLOCK : IN STD_LOGIC; RESET : IN STD_LOGIC; RK : IN STD_LOGIC_VECTOR(3 DOWNTO 1); DE : OUT STD_LOGIC_VECTOR(3 DOWNTO 1); Invalid_Key : OUT STD_LOGIC := '0'; Seg1 : OUT STD_LOGIC_VECTOR(7 Downto 0); Seg2 : OUT STD_LOGIC_VECTOR(7 Downto 0)
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