verilog spi master源码
module spi_master(sysclk,key,reset,mosi,miso,sclk,ss,led); input sysclk; input reset; input miso; input [1:0] key; output mosi; output ss; output sclk; output [1:0] led; // led????????? reg mosi; reg sclk; reg ss; reg en; // ???? reg [7:0] shifter; // ????? reg [1:0] cnt; // ????? reg [5:0] cnt1; reg [12:0] cnt2; reg [6:0] cnt3; reg [7:0] data; // ?????? reg [3:0] count; reg [4:0] addr; reg [1:0] key_buf1; // ??????? reg [1:0] key_buf2; reg [1:0] key_on_r; reg [1:0] key_on_rr; wire [1:0] key_on; // ??????????????????? wire clk5khz; wire sclk2; // ???sclk????? always @(posedge sysclk or negedge