riscv

问题 I'm having trouble debugging a simple program running in QEMU with GDB. GDB seems unable to find where I am in the program (in that it always displays ?? as my current location), and it never hits any breakpoint I set. In one terminal, I run QEMU: $ cat add.c int main() { int x = 9; int v = 1; while (1) { int q = x + v; } return 0; } $ riscv64-unknown-elf-gcc add.c -g $ qemu-system-riscv64 -gdb tcp::1234 -drive file=a.out,format=raw And in another terminal, I run GDB: $ riscv64-unknown-elf

问题 Can someone please help me out with this. There is a C-code which most of you are familiar with, it checks the endian-ness of a machine. What would be the result if it runs on a RISC-V machine? Code is mentioned as below: #include <cstdio> int main() { int x = 1; char* p = (char*)&x; printf("%d\n",(int)*p); return 0; } 回答1: The program is valid regardless of the platform. The output is 1 for a little-endian computer or a computer where sizeof (int) == sizeof (char) . It will be 0 for all

问题 I'm a new user of chisel. I tried to install chisel on my machine. According to the git, first I cloned chisel and then I went to hello directory and enter make . But I got the below error: set -e -o pipefail; sbt -Dsbt.log.noformat=true -DchiselVersion="latest.release" "run Hello --genHarness --compile --test --backend c --vcd " | tee Hello.out /bin/sh: 1: set: Illegal option -o pipefail make: *** [Hello.out] Error 2 I'm using sbt-0.13.8 and scala 2.11.6 回答1: If you try without the command

问题 For x86 and x64 compilers generate similar zero/sign extend MOVSX and MOVZX. The expansion itself is not free, but allows processors to perform out-of-order magic speed up. But on RISC-V: Consequently, conversion between unsigned and signed 32-bit integers is a no-op, as is conversion from a signed 32-bit integer to a signed 64-bit integer. A few new instructions (ADD[I]W/SUBW/SxxW) are required for addition and shifts to ensure reasonable performance for 32-bit values. (C) RISC-V Spec But at

问题 Currently, I'm learning RISC-V, use the RISC-V toolchain, and edit a new ld script for my embedded. I write a example, and compile to watch the opcode. Example: #include <stdio.h> //float.c int main() { float a=1.04; printf("a=%f\n",a); return 0; } My steps is: 1. riscv64-unknown-elf-gcc -S float.c　　*//generate assembly code* 2. riscv64-unknown-elf-as float.s -o float.o　　*//generate obj file* 3. riscv64-unknown-elf-ld -T elf64lriscv1.x float.o *//use own script to link, -T is using other

问题 I have a debugging script that does the following: sets two breakpoints. let's call them start and end breakpoints. after starting, the script continues until start breakpoint is hit. once start breakpoint is hit, I perform single-stepping until end breakpoint is hit. This is my command file: # end breakpoint break 38 commands stop 1 quit end # start breakpoint break 50 commands set logging off set logging file log.txt set logging overwrite on set logging on printf "program counter: $pc" end

问题 I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE: It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline 295: ifndef SYNTHESIS 296: PC_WB <= $random; 回答1: Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using `ifdef SYNTHESIS ... `endif blocks, as is done in this code. Xilinx XST does not define this macro by default, so you have to configure XST manually to

问题 I am interested in RISCV software tools, and have some knowledge in linux and toolchain. I want to setup riscv-tools on my system running in ubuntu 14.04 - 32 bit. I tried the steps given in github and the build failed. Is there any basic requirement for this build. Error log: configure: WARNING: decimal float is not supported for this target, ignored In file included from ../../../build-gcc-newlib-src/libgcc/../gcc/libgcc2.c:57:0: ../../../build-gcc-newlib-src/libgcc/../gcc/libgcc2.h:138:1:

问题 I have some question related the RISC V manual It has different types of instruction encoding such as R-type,I-type. Just like the MIPS encoding. * R-type 31 25 24 20 19 15 14 12 11 7 6 0 +------------+---------+---------+------+---------+-------------+ | funct7 | rs2 | rs1 |funct3| rd | opcode | +------------+---------+---------+------+---------+-------------+ * I-type 31 20 19 15 14 12 11 7 6 0 +----------------------+---------+------+---------+-------------+ | imm | rs1 |funct3| rd |

问题 I was reading source code of rocket chip, in rocc.scala file in rocket/src/main/scala/ there is an example AccumulatorExample for using rocc . At first part of the code there is a function Queue() that I couldn't figure out what it's doing? val n = 4 val regfile = Mem(UInt(width = params(XprLen)), n) val busy = Vec.fill(n){Reg(init=Bool(false))} val cmd = Queue(io.cmd) val funct = cmd.bits.inst.funct val addr = cmd.bits.inst.rs2(log2Up(n)-1,0) val doWrite = funct === UInt(0) val doRead =