riscv

问题 I have a trivial example C program:- #include <stdio.h> int main() { printf("hello world!"); return 1; } I use the following command to compile it and generate assembly:- riscv32-unknown-elf-gcc -S hello.c -o hello.asm Which generates the following assembly: - .file "hello.c" .option nopic .section .rodata .align 2 .LC0: .string "hello world!" .text .align 2 .globl main .type main, @function main: addi sp,sp,-16 sw ra,12(sp) sw s0,8(sp) addi s0,sp,16 lui a5,%hi(.LC0) addi a0,a5,%lo(.LC0) call

问题 I'm reading the book The RISC-V Reader: An Open Architecture Atlas . The authors, to explain the isolation of an ISA ( Instruction Set Architecture ) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is to include instructions in an ISA that helps performance or cost of one implementation at a particular time, but burden different or future implementations. As far as I understand, it states that when designing an ISA, the ISA should ideally

问题 After skimming the risc-v isa doc, it gives me the impression that the riscv supports both 16bits(RVC), 32bits(RV32I), 64bits(RV64I) length of instructions. For the RV32I: immediate is signed extented to 32 bits Instruction length:32 bits Register size: 32 bits Memory address: 32 bits For the RV64i: immediate is signed extented to 64 bits Instruction length:32 bits Register size: 64 bits Memory address: 64 bits It seems both RV32I & RV64I use 32 bits instruction size and the difference

问题 I want to boot linux of riscv-poky on ZedBoard. I've changed MACHINE to riscv64 in conf/local.conf, and created image via bitbake core-image-riscv . After that, I've checked that the linux is booted successfully on spike via runspike riscv64 . By the way, when I boot linux on ZedBoard with same vmlinux and rootfs, it is not running after printing the RISCV logo. The command is below: ./fesvr-zynq +disk=/sdcard/poky/core-image-riscv-riscv64.ext2 bbl /sdcard/poky/vmliux-riscv64.bin

问题 I have tried and failed a few times to install the riscv-gnu-toolchain into a virtual machine. Does anyone have a suggested Linux / virtual machine configuration (ideally a Vagrantfile)? If I can't find one, I'll make one myself and share it here. Starting OS version, memory and hard-drive capacity - ideally non-GUI, and as minimal as makes sense. Also, since it's such a huge build, are people having luck with multi-CPU setups and make -j6 (or your core-count) for parallel builds? 回答1: This

问题 LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. I found this in manual, but if I want to move 0xffffffff to a register, all the code I need is: LUI x2, 0xfffff000 ADDI x2, x2, 0xfff But a problem occurred, ADDI will extend sign to make a immediate data to a signed number, so 0xfff will be extend to 0xffffffff . It make x2 to

问题 I am trying to create a boot program for RISC-V based boards. I am following this guide, and adapting it for riscv. osdev The problem I'm having is translating this instruction. times 510 -( $ - $$ ) db 0 The best I could think of is to just fill 63ish lines of this .8byte 0 But this doesn't seem very feasible. Here is the Full code. ################################# ########### Boot Init ########### ################################# .section .text start: # begins the program nop # the do

问题 I want to make a multicore using zedboard. I have a 2 question about that. I changed a variable 'NTILES' to 2 in rocket-chip/src/main/scala/Configs.scala for implementing multicore system. If I make a multicore, how do I confirm that? I tried using fork and background execution to check the modified system, but I received error message like below picture. And pthreads couldn't be compiled. I want to know the method to confirm the multicore system. Also if you have any idea about making

问题 I've set up a hello world program just for testing my riscv32-unknown-elf toolchain, spike , pk etc. Though I managed to get the hello world printed using spike --isa=RV32 pk hello.elf , I found out that if I added the -d flag for debugging, I was given following instructions (a section of the whole): core 0: 0x0000000000001000 (0x7ffff297) auipc t0, 0x7ffff : core 0: 0x0000000000001004 (0x00028067) jr t0 : core 0: 0xffffffff80000000 (0x1b00006f) j pc + 0x1b0 : core 0: 0xffffffff800001b0

问题 In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there is a variants of S and U types which are SB and UJ which I suppose mean Branch and Jump as shown in figure 2.3. Then there is the types of Immediate produced by RISC-V instructions shown in figure 2.4. So my questions are, why the SB and UJ are needed? and why shuffle the Immediate bits in that way?