riscv

问题 I am trying to build a yocto demo-coreip-cli image for my custom risc-v SOC which only supports imafd instructions. For the compilation of cross toolchain that is used by Bitbake, I tried changing cross-binutils.inc recipe and cross-gcc.inc recipe in openembedded-core layer by including “ –with-arch=rv64imafd ” in " EXTRA_OECONF " variable. Is there anything else I am missing or doing wrong? Thank You. 回答1: I was able to successfully port the image to RV64-imafd. You can follow this link for

问题 I am trying to create an Immediate Generator for RISC-V assembly but I have encountered with if statement. Here is my code in Verilog: module signextend(in, out, sel); parameter nin = 32; parameter nout = 32; input [nin-1:nin-25] in; input [2:0] sel; output [nout-1:0] out; if (sel == 3'b000) begin assign out[19:0] = in[31:12]; assign out[31:20] = {12{in[31]}}; end else if (sel == 3'b001) begin assign out[11:0] = in[31:20]; assign out[31:12] = {20{in[31]}}; end else if (sel == 3'b010) begin

来源： https://stackoverflow.com/questions/50214840/risc-v-startup-code-for-stack-pointer-initalization

问题 Most instructions in RISC-V assembler order the destination operand before the source one, e.g.: li t0, 22 # destination, source li t1, 1 # destination, source add t2, t0, t1 # destination, source But the store instructions have that order reversed: sb t0, (sp) # source, destination lw t1, (a0) # destination, source vlb.v v4, (a1) # destination, source vsb.v v5, (a2) # source, destination How come? What is the motivation for this (arguably) asymmetric assembler syntax design? 回答1: I don't see

问题 When I reading RISC-V User-Level ISA manual,I noticed that it said that "OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations." so RISC-V don't have branch delay slot RISC-V User-Level ISA manual link. Moreover,Wikipedia said that most of newer RISC design omit branch delay slot. Why most of newer RISC Architecture gradually omit branch delay slot? 回答1: Citing Henessy and Patterson (Computer architecture and design, 5th ed.) Fallacy : You

问题 What is the simplest way to work with big-endian values in RISC-V at the assembly language level? That is, how to load a big-endian value from memory into a register, work with the register value in native-endian (little-endian), then store it back into memory in big-endian. 16, 32 and 64 bit values are used in many network protocols and file formats. I couldn't find a byte-swap instruction (equivalent to BSWAP on x86 or REV on ARM) in the manual, nor anything about big-endian loads and

问题 I am trying to loop through an array and if the number is larger than X then print. I've tried to find tutorials online but I'm just stuck on why it is not working/outputting anything. My comments kind of explain what i tried to do. .data arrayOfNums: .word 0 .word 1 .word 122 .word 1112 .word 4294967295 .word 22 .word 234234 .word 23332 .word 42 .word 23423 K: .word 2237 .text .globl main main: #### *** vv My problem starts here vv *** #### la t0 K #set t0 to K la t1 arrayOfNums #set t1

问题 I'm trying to get remote debugging working in QEMU for the sifive_u machine. All tools are from the Arch Linux repositories: ➜ qemu-system-riscv64 --version QEMU emulator version 4.2.0 Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers ➜ riscv64-linux-gnu-gdb --version GNU gdb (GDB) 8.3.1 Copyright (C) 2019 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and

问题 I am reading a book "Computer Organization and Design RISC-V Edition" , and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field into 2 parts. This makes sense since all instructions encoding has to be similar. But I cannot understand why the immediate field is encoded in this way below. imm[12, 10:5], imm[4:1, 11] instead of imm[11:5], imm[4:0] U-J types also have this

问题 I am reading a book "Computer Organization and Design RISC-V Edition" , and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field into 2 parts. This makes sense since all instructions encoding has to be similar. But I cannot understand why the immediate field is encoded in this way below. imm[12, 10:5], imm[4:1, 11] instead of imm[11:5], imm[4:0] U-J types also have this