riscv

问题 I am looking for how a RISC-V processor processes interrupt requests. I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title sets: the instruction set. In my view, how interrupts are handled is a question of what is called the "programmer's model" of the processor. It does not clearly fit into a document about an instruction set, because parts of interrupt processing are not expressed in instructions. Clearly, jumping into an

问题 Now, I'm implemented an ASP (Application Specific Processor) and I want to develop it with an RISC-type architecture. Reading a bit on the web, I concluded that the best option is to use RISC-V. The idea is to develop a design in Verilog so that it can run the RISC-V ISA. And the software application that the processor should run is very simple, only a few arithmetic operations. For this reason as it is only one application it is not necessary that the processor supports an operating system.

问题 In Control and Status Registers section of riscv-asm-manual, there is an example: .equ RTC_BASE, 0x40000000 .equ TIMER_BASE, 0x40004000 # setup machine trap vector 1: auipc t0, %pcrel_hi(mtvec) # load mtvec(hi) addi t0, t0, %pcrel_lo(1b) # load mtvec(lo) csrrw zero, mtvec, t0 ... # break on interrupt mtvec: csrrc t0, mcause, zero bgez t0, fail # interrupt causes are less than zero slli t0, t0, 1 # shift off high bit ... I guess %pcrel_hi(mtvec) calculate the hi-distance between mtvec and

问题 I was trying to read RISC-V assembly generated by gcc and I found that gcc creates sequence of auipc + jalr for some function calls and I don't understand how it works. Here's a simple example. Consider the following C source file: unsigned long id(unsigned long x) { return x; } unsigned long add_one(unsigned long x) { return id(x)+1; } I compile it with gcc -O2 -fno-inline -c test.c and I get the following assembly code: $ objdump -d test.o test.o: file format elf64-littleriscv Disassembly

问题 I'm confused about the RISC-V ABI Register Names. For example, Table 18.2 in the "RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" at page 85 specifies that the stack pointer sp is register x14 . However, the instruction addi sp,zero,0 is compiled to 0x00000113 by riscv64-unknown-elf-as ( -m32 does not make a difference). In binary: 000000000000 00000 000 00010 0010011 ^imm ^rs1 ^f3 ^rd ^opcode So here sp seems to be x2 . Then I googled a bit and found the RISC-V Linux

问题 In the RISC-V specification, it is written that the immediates in JAL and JALR instructions are converted to jump offsets as : Sign extend the given immediate to XLEN bits. Set the LSB to zero. I have a couple of questions regarding this. QUESTION 1 For JAL, this gives a range : 000000000000 to 111111111110 that is, 4KiB. Here, if the LSB is going to have to be zero always, why isn't the immediate just considered as the 12 bits before a mandatory zero LSB for the address, hence increasing the

问题 I was reading the source code of RISC-V test pattern. And there is a macro define in riscv-test.h, I want to know what does 1: means in this code: #define RVTEST_CODE_BEGIN \ .section .text.init; \ .align 6; \ .weak stvec_handler; \ .weak mtvec_handler; \ .globl _start; \ _start: \ /* reset vector */ \ j reset_vector; \ .align 2; \ trap_vector: \ /* test whether the test came from pass/fail */ \ csrr t5, mcause; \ li t6, CAUSE_USER_ECALL; \ beq t5, t6, write_tohost; \ li t6, CAUSE_SUPERVISOR

问题 How do I write NOT Operation for the Risc-V (Assembly Language)? If there's no NOT instruction, how do you achieve the same thing? 回答1: Like MIPS and some other architectures, RISC V does not provide dedicated instructions for many things, including two-operand unary operations, as these operations can be had using their three-operand format, usually with x0 as the third operand, but sometimes constant 1 or -1 as the third operand. For convenience, the assembler will accept what are called

问题 How do I write NOT Operation for the Risc-V (Assembly Language)? If there's no NOT instruction, how do you achieve the same thing? 回答1: Like MIPS and some other architectures, RISC V does not provide dedicated instructions for many things, including two-operand unary operations, as these operations can be had using their three-operand format, usually with x0 as the third operand, but sometimes constant 1 or -1 as the third operand. For convenience, the assembler will accept what are called

问题 I find that in RISC-V, ra is caller saved, in MIPS, ra is callee, which means in RISC-V callee can directly change the value in ra without save, but since ra has changed, how callee return back to caller? 回答1: The usage of RISC V ra and MIPS $ra is effectively the same regardless of the designation. Since both caller (who needs to return to their caller) and (a non-leaf) callee need to repurpose the return address register, the value in that register needs to be preserved. The only logical