rdtsc

As a follow-up to this topic , in order to calculate the memory miss latency, I have wrote the following code using _mm_clflush , __rdtsc and _mm_lfence (which is based on the code from this question/answer ). As you can see in the code, I first load the array into the cache. Then I flush one element and therefore the cache line is evicted from all cache levels. I put _mm_lfence in order to preserve the order during -O3 . Next, I used time stamp counter to calculate the latency or reading array[0] . As you can see between two time stamps, there are three instructions: two lfence and one read .

Suppose all the cores in my CPU have same frequency, technically I can synchronize system time and time stamp counter pairs for each core every millisecond or so. Then based on the current core I'm running with, I can take the current rdtsc value and using the tick delta divided by the core frequency I'm able to estimate the time passed since I last synchronized the system time and time stamp counter pair and to deduce the current system time without the overhead of system call from my current thread (assuming no locks are needed to retrieve the above data). This works great in theory but in

I'm looking into measuring benchmark performance using the time-stamp register (TSR) found in x86 CPUs. It's a useful register, since it measures in a monotonic unit of time which is immune to the clock speed changing. Very cool. Here is an Intel document showing asm snippets for reliably benchmarking using the TSR, including using cpuid for pipeline synchronisation. See page 16: http://www.intel.com/content/www/us/en/embedded/training/ia-32-ia-64-benchmark-code-execution-paper.html To read the start time, it says (I annotated a bit): __asm volatile ( "cpuid\n\t" // writes e[abcd]x "rdtsc\n\t"

This question already has an answer here: How to get the CPU cycle count in x86_64 from C++? 4 answers With Visual Studio I can read the clock cycle count from the processor as shown below. How do I do the same thing with GCC? #ifdef _MSC_VER // Compiler: Microsoft Visual Studio #ifdef _M_IX86 // Processor: x86 inline uint64_t clockCycleCount() { uint64_t c; __asm { cpuid // serialize processor rdtsc // read time stamp counter mov dword ptr [c + 0], eax mov dword ptr [c + 4], edx } return c; } #elif defined(_M_X64) // Processor: x64 extern "C" unsigned __int64 __rdtsc(); #pragma intrinsic(_

Assume we're trying to use the tsc for performance monitoring and we we want to prevent instruction reordering. These are our options: 1: rdtscp is a serializing call. It prevents reordering around the call to rdtscp. __asm__ __volatile__("rdtscp; " // serializing read of tsc "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up "or %%rdx,%%rax" // and or onto rax : "=a"(tsc) // output to tsc variable : : "%rcx", "%rdx"); // rcx and rdx are clobbered However, rdtscp is only available on newer CPUs. So in this case we have to use rdtsc . But rdtsc is non-serializing, so using it alone will

On recent CPUs (at least the last decade or so) Intel has offered three fixed-function hardware performance counters, in addition to various configurable performance counters. The three fixed counters are: INST_RETIRED.ANY CPU_CLK_UNHALTED.THREAD CPU_CLK_UNHALTED.REF_TSC The first counts retired instructions, the second number of actual cycles, and the last is what interests us. The description for Volume 3 of the Intel Software Developers manual is: This event counts the number of reference cycles at the TSC rate when the core is not in a halt state and not in a TM stop-clock state. The core