program-counter

问题 As we always know the procedure of executing task by a microprocessor is just executing binary instructions from memory one by one and there is a program counter which holds the address of the next instruction. So this is how processor executes it's tasks if I am not wrong. But there is also another pointer named Stack Pointer which does almost same thing like the program counter. My question is why we need a Stack Pointer to point address of memory(Stack)? Can somebody tell me about the main

来源： https://stackoverflow.com/questions/64092889/how-is-code-stored-and-executed-on-the-c-abstract-machine

问题 I'm reading the book The RISC-V Reader: An Open Architecture Atlas . The authors, to explain the isolation of an ISA ( Instruction Set Architecture ) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is to include instructions in an ISA that helps performance or cost of one implementation at a particular time, but burden different or future implementations. As far as I understand, it states that when designing an ISA, the ISA should ideally

问题 Trying to understand the cause of the watchdog. The snippet of assembly routine is as follows: fe813cf0: 2820 cmp r0, #32 fe813cf2: dbf0 blt.n fe813cd6 <XYZ+0x10> fe813cf4: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff fe813cf8: bd10 pop {r4, pc} My PC value from dump is fe813cf3. What does this mean? How should I interpret it? Please let me know if more info is required. 回答1: If it's a watchdog that triggers, that seems to indicate that the processor has hung. The state you're capturing might

问题 Until now I thought that a 32-bit processor can use 4 GiB of memory because 2 32 is 4 GiB, but this approach means processor have word size = 1 byte . So a process with 32-bit program counter can address 2 32 different memory words and hence we have 4 GiB. But if a processor has word size larger than 1 byte , which is the case with most of processors now days I believe ( My understanding is that word size is equal to the width of data bus, so a processor with 64-bit data bus must have a word

问题 I read in a book that in a wavefront or warp, all threads share a common program counter. So what is its consequence? Why does that matter? 回答1: NVIDIA GPUs execute 32-threads at a time (warps) and AMD GPUs execute 64-threads at time (wavefronts). The sharing of control logic, fetch, and data paths reduces area and increases perf/area and perf/watt. In order to take advantage of the design programming languages and developers need to understand how to coalesce memory accesses and how to

问题 I want to take a piece of code, copy it into a global array and execute it from there. In other words, I am trying to to copy a bunch of instructions from the code-section into the data-section, and then set the program-counter to continue the execution of the program from the data-section. Here is my code: #include <stdio.h> #include <string.h> typedef void(*func)(); static void code_section_func() { printf("hello"); } #define CODE_SIZE 73 // I verified this size in the disassembly of 'code

问题 I'm trying to track the value of the PC of a particular process within the kernel. To do this, I looked at the kernel source and figured out that the pc is being stored inside task_struct->stack and that to make sense of the stack, I need to type cast it into struct thread_info * . Therefore, in in gdb, I set a breakpoint b scheduler_tick (called every 10ms). However, when I printed out p/x ((struct thread_info *)curr->stack)->cpu_context.pc , I received the value as $4 = 0x804d19d8 . I

问题 Hi I am wondering where the program counter goes when the program returns from interrupt service routine? I know when the interrupt event occurs the PC is pushed into the stack. But what address is pushed into the stack the next one or the same one(just executed one)?When we have first instruction; interrupt event here; go inside the ISR; exit ISR; second instruction; OR first instruction; interrupt event here; go inside the ISR exit ISR; first instruction; I mean, does the PC points to the

问题 Program counter holds the address of the instruction that should be executed next, while instruction register holds the actual instruction to be executed. wouldn't one of them be enough? And what is the length of each one of these registers? Thanks. 回答1: You will need both always. The program counter (PC) holds the address of the next instruction to be executed, while the instruction register (IR) holds the encoded instruction. Upon fetching the instruction, the program counter is incremented