opcode

问题 I just started learning assembly programming. I am using NASM on linux. I wrote this code that's basically meant to calculate the somethingth power of something and I know it's probably not exactly good, but I really don't care at this point, all I want is just SOME idea why I keep getting that error, because I have tried to modify and switch operands and operations and everything in the section where the problem is, but if anything that only gave me more error messages. As I said, I'm really

问题 I just started learning assembly programming. I am using NASM on linux. I wrote this code that's basically meant to calculate the somethingth power of something and I know it's probably not exactly good, but I really don't care at this point, all I want is just SOME idea why I keep getting that error, because I have tried to modify and switch operands and operations and everything in the section where the problem is, but if anything that only gave me more error messages. As I said, I'm really

问题 looking at http://ref.x86asm.net/coder32.html I found two opcodes that match for the statement xor eax,eax 1) opcode 31 XOR r/m16/32 r16/32 2) opcode 33 XOR r16/32 r/m16/32 both refers to 32bit register for operand1 and operand2. So, is there any differences in this specific case of the XORing two 32bit registers ? 回答1: x86 has 2 redundant ways to encode a 2-register instance of any of the basic ALU instructions that have r/m source and r/m destination forms. This redundancy is a consequence

问题 The op code portion of many important x86 instructions like MOV and ADD has the last two bits standardized as a direction bit and a data size bit: Is there any pattern to the part of the op code shown in gray here? For example, for ADD some of the instructions use the code 000000 and others have code 100000. 来源： https://stackoverflow.com/questions/41720529/is-there-a-pattern-to-x86-op-codes-other-than-direction-and-size-bits

问题 By looking at intel volume of instructions, I found this: 1) 88 /r MOV r/m8,r8 2) 8A /r MOV r8,r/m8 When I write a line like this in NASM, and assemble it with the listing option: mov al, bl I get this in the listing: 88D8 mov al, bl So obviously NASM chosed the first instruction of the two above, but isn't the second instruction an option two? if so, on what basis did NASM chosed the first? 回答1: These two encodings exist because a modr/m byte can only encode one memory operand. So to allow

问题 My question arises from a simple curiosity: Why in x64 some of the opcodes are invalid (06, 07 for example), whereas in x86 are used for fairly basic instructions (06 and 07 being push and pop)? I though that those simplest instructions would do nicely in both architectures. Why they disabled some of those simple instructions in x64? Why wouldn't they work? Why they disabled some opcodes, creating holes in opcode list, when they could instead assign them to x64 versions of instructions?

问题 This might be a really strange question, but I have been doing some work on the little man computer and it mildly annoys me that not only is there no operation code number 4, but there is absolutely no information on the internet as to why. The opcodes go 0-9 but skip 4. Are there never any three digit codes that start with 4? What happens if there is? Is there anyone out there that would be able to help answer this question? I just find it so strange. Thank you! 回答1: The Little Man Computer

问题 I know that there are libraries that can "parse" binary machine code / opcode to tell the length of an x86-64 CPU instruction. But I'm wondering, since CPU has internal circuitry to determine this, is there a way to use processor itself to tell the instruction size from a binary code? (Maybe even a hack?) 回答1: The Trap Flag (TF) in EFLAGS/RFLAGS makes the CPU single-step, i.e. take an exception after running one instruction. So if you write a debugger, you can use the CPU's single-stepping

问题 I know that there are libraries that can "parse" binary machine code / opcode to tell the length of an x86-64 CPU instruction. But I'm wondering, since CPU has internal circuitry to determine this, is there a way to use processor itself to tell the instruction size from a binary code? (Maybe even a hack?) 回答1: The Trap Flag (TF) in EFLAGS/RFLAGS makes the CPU single-step, i.e. take an exception after running one instruction. So if you write a debugger, you can use the CPU's single-stepping

问题 I know that there are libraries that can "parse" binary machine code / opcode to tell the length of an x86-64 CPU instruction. But I'm wondering, since CPU has internal circuitry to determine this, is there a way to use processor itself to tell the instruction size from a binary code? (Maybe even a hack?) 回答1: The Trap Flag (TF) in EFLAGS/RFLAGS makes the CPU single-step, i.e. take an exception after running one instruction. So if you write a debugger, you can use the CPU's single-stepping