neon

问题 I'm trying to optimize an image format conversion on iOS using the NEON vector instruction set. I assumed this would map well to that because it processes a bunch of similar data. My attempts haven't gone that well, though, achieving only a marginal speedup vs the naive c implementation: for(int i = 0; i < pixelCount; ++i, ++inPixel32) { const unsigned int r = ((*inPixel32 >> 0 ) & 0xFF); const unsigned int g = ((*inPixel32 >> 8 ) & 0xFF); const unsigned int b = ((*inPixel32 >> 16) & 0xFF);

问题 I want to calculate the magnitude and the angle of 4 points using neon instructions SIMD and arm assembly. There is a built in library in most languages, C++ in my case, which calculates the angle (atan2) but for only one pair of floating point variables (x and y). I would like to exploit SIMD instructions that deal with q registers in order to calculate atan2 for a vector of 4 values. The accuracy is required not to be high, the speed is more important. I already have a few assembly

问题 I'm trying to understand the comment made by "Iwillnotexist Idonotexist" at SIMD optimization of cvtColor using ARM NEON intrinsics: ... why you don't use the ARM NEON intrisics that map to the VLD3 instruction? That spares you all of the shuffling, both simplifying and speeding up the code. The Intel SSE implementation requires shuffles because it lacks 2/3/4-way deinterleaving load instructions, but you shouldn't pass on them when they are available. The trouble I am having is the solution

问题 Here is a C++ code: #define ARR_SIZE_TEST ( 8 * 1024 * 1024 ) void cpp_tst_add( unsigned* x, unsigned* y ) { for ( register int i = 0; i < ARR_SIZE_TEST; ++i ) { x[ i ] = x[ i ] + y[ i ]; } } Here is a neon version: void neon_assm_tst_add( unsigned* x, unsigned* y ) { register unsigned i = ARR_SIZE_TEST >> 2; __asm__ __volatile__ ( ".loop1: \n\t" "vld1.32 {q0}, [%[x]] \n\t" "vld1.32 {q1}, [%[y]]! \n\t" "vadd.i32 q0 ,q0, q1 \n\t" "vst1.32 {q0}, [%[x]]! \n\t" "subs %[i], %[i], $1 \n\t" "bne

问题 The ARM reference manual doesn't go into too much detail into the individual instructions ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0348b/BABIIBBG.html ). Is there something that's a little more detailed? 回答1: For more information on the instructions themselves, you need the Assembler Guide. The list you found there just shows the mapping from compiler intrinsics to assembly instructions. 回答2: There's also the ARM C Language Extensions which provides details on the

问题 I decided to continue Fast corners optimisation and stucked at _mm_movemask_epi8 SSE instruction. How can i rewrite it for ARM Neon with uint8x16_t input? 回答1: I know this post is quite outdated but I found it useful to give my (validated) solution. It assumes all ones/all zeroes in every lane of the Input argument. const uint8_t __attribute__ ((aligned (16))) _Powers[16]= { 1, 2, 4, 8, 16, 32, 64, 128, 1, 2, 4, 8, 16, 32, 64, 128 }; // Set the powers of 2 (do it once for all, if applicable)

问题 Im currently using some functions from the vDSP framework, especially the vDSP_conv and I'm wondering if there is any way to check if the function invokes scalar mode or is processed SIMD on the neon processor. The documentation of the function mentions some criteria for power-pc-architecture which have to be fulfilled or scalar mode is invoked. Now i neither know if these criteria apply for the iphone as well nor how to check if my function invokes scalar mode or runs properly on neon. is

问题 I want to take care the border conditions while handling any filters in image processing .I am extrapolating the border and creating the new boundary.For example I am having 4x3 input : //Input int image[4][3] = 1 2 3 4 2 4 6 8 3 6 9 12 //Output int extensionimage[6][5] = 1 1 2 3 4 4 1 1 2 3 4 4 2 2 4 6 8 8 3 3 6 9 12 12 3 3 6 9 12 12 My code : #include <stdio.h> #include <string.h> #include <stdlib.h> void padd_border(int *img,int *extension,int width,int height); int main(){ int width = 4

问题 I'm trying to figure out how to generate a conditional Store in ARM neon. What I would like to do is the equivalent of this SSE instruction: void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p); which Conditionally stores byte elements of d to address p.The high bit of each byte in the selector n determines whether the corresponding byte in d will be stored. Any suggestion on how to do it with NEON intrinsics? Thank you This is what I did: int8x16_t store_mask = {0,0,0,0,0,0,0xff,0xff,0xff

问题 What exactly will happen with below 2 lines of code? vst1.64 {d8, d9, d10, d11}, [r4:128]! vst1.64 {d12, d13, d14, d15}, [r4:128] More generally, I want to know what VST & VLD do since doc from: ARM InfoCenter doesn't make it clear for me. 回答1: vst1.64 {d8, d9, d10, d11}, [r4:128]! This instruction stores the content of the registers d8, d9, d10 and d11 at the location pointed by r4. This location is hinted to be aligned to a 128 bit boundary. Afterwards r4 will be incremented by the amount