kbuild

I'm trying to compile a linux kernel module using a Makefile: obj-m += main.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean Which gives me: main.c:54: warning: ISO C90 forbids mixed declarations and code I need to switch to C99. After reading I noticed I need to add a flag -std=c99, not sure where it suppose to be added. How do I change the Makefile so it will compile as C99? It's got nothing to do with the makefile. ISO C90 forbids declaring variables anywhere but in the beginning of a block or the file -

I have done make menuconfig for a board defconfig and modified few configurations. When I select save, a new .config was created in the Kernel top directory. I want to create new defconfig for this .config file created. Can I copy the .config as a new defconfig and copy to arch/arm/configs/ ? $ cp .config arch/arm/configs/board_new_defconfig 0andriy I think you have to do just one command and use the created file as you want to. % make savedefconfig % cp defconfig arch/arm/configs/my_cool_defconfig To get all possible targets just run % make help As noted by Adam Miller followed by Jeremy ,

When i'm developing a linux driver, i've read about how to write linux kbuild makefile through this document I know kbuild system use makefile variables such as obj-y obj-m to determine what to build and how to build. But what i'm confused about is where does kbuild system really execute build process.In a word, if i have obj-m = a.o , then where does kbuild system parse obj-m and execute gcc a.c ? Kbuild's Makefiles aren't the easiest to read, but here's a high-level untangling (using the 4.0-rc3 kernel): The top-level Makefile does include $(srctree)/scripts/Kbuild.include , where $(srctree)

I'm trying to link my kernel module with an external static lib, like this: obj-m += my_prog.o my_prog-objs := some/path/lib.a # all the standard targets... For some reasone, the above Makefile doesn't compile my_prog.c at all, and the resulting module doesn't contain its code. Certainly, if I remove my_prog-objs line, my_prog.c gets compiled. What's wrong with such an approach in a Makefile? When you create the my_prog-objs list, you tell kbuild to use only the object files in that list. kbuild will no longer compile my_prog.c , and including my_prog.o in my_prog-objs results in a circular

I can use the following command to create a Linux kernel .config file based on a specified architecture default for a custom ARM-based board: ARCH=arm make defconfig KBUILD_DEFCONFIG=var_som_mx6_android_defconfig I thought that this command more or less copies ./arch/arm/configs/var_som_mx6_android_defconfig to ./.config . However the resulting .config file isn't exactly a copy: $ diff --unified arch/arm/configs/var_som_mx6_android_defconfig .config --- arch/arm/configs/var_som_mx6_android_defconfig 2017-01-20 12:10:51.891515984 -0800 +++ .config 2017-01-26 15:31:29.000000000 -0800 @@ -407,6

I'm confronting the Linux kernel build system (Kbuild, kernel ≥2.6.28) with the directory structure and build system for a larger project. Our project contains an out-of-tree Linux kernel module, and our directory structure looks like this (simplified, obviously): checkout/src/common/*.c source files (common to Linux and other platforms) checkout/src/linux-driver/*.c source files (for the Linux kernel driver) checkout/build/linux/Kbuild Kbuild tmp/linux-2.6.xx/ where the Linux kernel is unpacked and configured output/linux-arm-debug/ where object files must end up The build process must not