intel-tsx

问题 I am using glibc 2.24 version. It has lock elision path included for pthread_mutex_lock implementation with Transactional Synchronization Extensions such as _xbegin() and _xend(). The hardware is supposed to support lock elision as hle CPU flag is for Hardware Lock Elision I think. The processor I am using is Intel(R) Xeon(R) Gold 6130 with Skylake architecture. First I wanted to disable Lock elision but when I run the program that uses pthread_mutex_lock , with perf stat -T to monitor

问题 I am using glibc 2.24 version. It has lock elision path included for pthread_mutex_lock implementation with Transactional Synchronization Extensions such as _xbegin() and _xend(). The hardware is supposed to support lock elision as hle CPU flag is for Hardware Lock Elision I think. The processor I am using is Intel(R) Xeon(R) Gold 6130 with Skylake architecture. First I wanted to disable Lock elision but when I run the program that uses pthread_mutex_lock , with perf stat -T to monitor

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when I attempt to run it on AMD machines? Intel says that these were designed to be backwards compatible, presumably meaning they do nothing on Intel CPUs without TSX. I know that AMD has not implemented TSX. But are these prefixes safe to run on AMD

问题 I think C++ does not cover any sort of transaction memory yet, but still TSX can somehow fit using " as if rule" into something that is governed by C++ memory model. So, what happens on successful HLE operation, or successful RTM transaction? Saying "there is data race, but it is ok" is not much helpful, as it does not clarify what "ok" means. With HLE probably it can be seen as "previous operation happens before subsequent operation. As if the section was still guarded by the lock that was

问题 It seems that Intel's Transactional Synchronization Extensions (TSX-NI) work on a per-CPU basis. This applies to both the _InterlockedXxx_HLE{Acquire,Release} Hardware Lock Elision functions (HLE), as well as for the _xbegin / _xend /etc. Restricted Transactional Memory (RTM) functions. What is the "proper" way to use these functions on multi-core systems? Given their correctness guarantees, I assume I only need to be worried about performance here. So, how should I structure & write my code

问题 From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever. But when a transaction aborts, it would be good to see what address - or cache line - caused it (when such a thing was the reason for the abort). Is the address exposed anywhere? 回答1: After talking to folks at Intel, there is no way to do this [citation]. The address is

问题 From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever. But when a transaction aborts, it would be good to see what address - or cache line - caused it (when such a thing was the reason for the abort). Is the address exposed anywhere? 回答1: After talking to folks at Intel, there is no way to do this [citation]. The address is

问题 Is this correct that Hardware Lock Elision is disabled for all current CPUs due to Spectre mitigation, and any attempt to have a mutex using HLE intrinsics/instructions would result in usual mutex? Is this likely that there will not be anything like HLE mutexes in future to avoid vulnerabilities like Spectre? 回答1: So, TSX may be disabled not to mitigate Spectre, but as a part of another vulnerability mitigation, TSX Asynchronous Abort (TAA). Here's relevant article on Intel website: Intel®