intel-fpga

Altera Quartus Error (12007): Top-level design entity “alt_ex_1” is undefined

感情迁移 提交于 2019-11-30 10:05:00
I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows: library ieee; use ieee.std_logic_1164.all; entity light is port(x1, x2: in std_logic; f: out std_logic); end light; architecture LogicFunction of light is begin f <= (x1 and not x2) or (not x1 and x2); end LogicFunction; I followed the project creation steps in the Altera tutorial , but when I try to compile the project I get the error: Error

ModelSim-Altera error

筅森魡賤 提交于 2019-11-30 04:30:23
问题 I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by Altera. Honestly, I don't have much of experience with simulation software like ModelSim-Altera but I do know how to use .vwf files and simulate with them, I know as well how to use signaltap logic analyzer. After creating the usinversity program

Compiling *.vhdl into a library, using Altera Quartus II

安稳与你 提交于 2019-11-29 14:57:56
I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: http://www.vhdl.org/fphdl/ , now available at http://web.archive.org/web/20160305202256/http://www.vhdl.org/fphdl/ In their user guide, below is mentioned: 'fixed_float_types_c.vhdl', 'fixed_pkg_c.vhdl' and 'float_pkg_c.vhdl' should be compiled into a library called "ieee_proposed". However, I do not exactly know how I can compile the mentioned *.vhdl files into a library using Altera

Altera Quartus Error (12007): Top-level design entity “alt_ex_1” is undefined

点点圈 提交于 2019-11-29 14:44:42
问题 I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows: library ieee; use ieee.std_logic_1164.all; entity light is port(x1, x2: in std_logic; f: out std_logic); end light; architecture LogicFunction of light is begin f <= (x1 and not x2) or (not x1 and x2); end LogicFunction; I followed the project