Altera Quartus Error (12007): Top-level design entity “alt_ex_1” is undefined
I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows: library ieee; use ieee.std_logic_1164.all; entity light is port(x1, x2: in std_logic; f: out std_logic); end light; architecture LogicFunction of light is begin f <= (x1 and not x2) or (not x1 and x2); end LogicFunction; I followed the project creation steps in the Altera tutorial , but when I try to compile the project I get the error: Error