intel-fpga

问题 I can't use Quartus 14.1.0 with Linux Debian (wheezy and Jessie) on my 64 bits computer. If I launch it on console I've got this message : user@fpgaformation:/opt/altera/14.1/quartus/bin$ ./quartus Inconsistency detected by ld.so: dl-close.c: 743: _dl_close: Assertion `map->l_init_called' failed! And the GUI is launched correctly. But, after some minutes of using it, quartus disappear suddenly without message on terminal but with an altera problem-window. In this window, we can get the

问题 input [31:0] write_data; input [4:0] write_reg; reg [31:0] registers [31:0]; always @(*) assign registers[write_reg] = write_data; I have a 32-bit input write_data , which i want to an assign corresponding index which i get from write reg.Error says you cant do continuous assignment which i think causes by always@(*) but if i remove that It says object "registers" on left-hand side of assignment must have a net type and its another error. 回答1: assign inside an always block is the procedural

问题 I just bought a new Cyclone V board from Terasic ( Atlas-SoC ) and planned to build a bare metal application. At first, I used the GSRD provided by Terasic. The example project is from version 14.0 and my 17.1 Quartus asked me to launch an update to those 14.0 IP, but I saw that they already compile everything and I had a handoff file folder. All I needed to do was just make a preloader and uboot. Then I followed these steps (from rocketboard and many places else): Generate .rbf file. I made

问题 im pretty new to the vhdl language so please bear with me. I just did the vhdl code for a 1 bit adder, but I am having trouble writing for the 4bit adder. This is what I got so far, if anybody could point me in the right direction of what to look up that would be awesome! VHDL code: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Adder4 IS GENERIC(CONSTANT N: INTEGER := 4); PORT( a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Input SW[7..4]: a[3..0] inputs, -- SW[3..0]: b[3..0] sum: OUT STD

问题 I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram array: dataout <= temp_ram(conv_integer(dir)); Then I want to divide the vaules of dataout to put in the seven segment dataout(7 downto 4) dataout(3 downto 0) This shows the following error: Error (10309): VHDL Interface Declaration error in RAM.vhd(45):

问题 What are .rbf files and how can i generate them from the Quartus output file .sof on windows ? 回答1: With Quartus II GUI go to File => Convert Programming Files, where .rbf can then be selected as output file, and the .sof can be given as input file. The conversion setup can be saved from the GUI for use in a command line like > quartus_cpf -c convert_sof_to_rbf.cof 回答2: An RBF is a " Raw Binary File ". It represents the raw data that will, for example, be loaded into a flash memory for

问题 I am trying to implement a Low Pass Filter in an FPGA using VHDL. Now, I worked out all the filter coefficients, but I am having trouble trying to understand how to work with the coefficients, given the fact that they are non-whole numbers. I would appreciate any help with an example of a simple filter implementation in VHDL. Thanks a lot, Chris 回答1: You should convert the coefficients to fix-point numbers. Very short: Chose a precision and multiply all coefficients by the nearest higher

问题 I am new to OpenCL. When I tried the examples from the website of Altera, I got several LNK2001 errors as follows Severity Code Description Project File Line Error LNK2001 unresolved external symbol __imp_sprintf hello_world C:\Users\S_KW\OpenCL\hello_world\alteracl.lib(acl_hal_mmd.obj) 1 Error LNK2001 unresolved external symbol __imp___iob_func hello_world C:\Users\S_KW\OpenCL\hello_world\alteracl.lib(acl_hal_mmd.obj) 1 Error LNK2001 unresolved external symbol __imp_fprintf hello_world C:

问题 I am new to OpenCL. When I tried the examples from the website of Altera, I got several LNK2001 errors as follows Severity Code Description Project File Line Error LNK2001 unresolved external symbol __imp_sprintf hello_world C:\Users\S_KW\OpenCL\hello_world\alteracl.lib(acl_hal_mmd.obj) 1 Error LNK2001 unresolved external symbol __imp___iob_func hello_world C:\Users\S_KW\OpenCL\hello_world\alteracl.lib(acl_hal_mmd.obj) 1 Error LNK2001 unresolved external symbol __imp_fprintf hello_world C:

问题 I want to generate delay using counter, actually here I use counter to generate delay after each 1 Bit transfer, so that its better understand externally on fpga pin from which by SPI(serial) LCD is connected with it. Therefore I had created a shift register which shift 1 bit then gives delay then next bit(Bit-Delay-bit-delay..). Here is my code of counter: module spidelay( input wire clk, input wire enb, output reg sclkout ); reg [23:0] stmp; always @(posedge clk) begin if ( enb == 1 ) begin