instruction-set

问题 They're one of the simplest "instructions" you could perform on a computer (they're the first ones I'd personally implement) Performing NOT(AND(x, y)) doubles execution time AND dependency chain length AND code size BMI1 introduced "andnot" which is a meaningful addition that is a unique operation - why not the ones in the title of this question? You usually read answers among the lines of "they take up valuable op-code space" but then I look at all of the kmask operations introduced with

问题 They're one of the simplest "instructions" you could perform on a computer (they're the first ones I'd personally implement) Performing NOT(AND(x, y)) doubles execution time AND dependency chain length AND code size BMI1 introduced "andnot" which is a meaningful addition that is a unique operation - why not the ones in the title of this question? You usually read answers among the lines of "they take up valuable op-code space" but then I look at all of the kmask operations introduced with

问题 I've got an application that requires AVX2 to work correctly. A check was implemented to check during application start if CPU has AVX2 instruction. I would like to check if it works correctly, but i only have CPU that has AVX2. Is there a way to temporarly turn it off for testing purposes? Or to somehow emulate other CPU? 回答1: Yes, use an "emulation" (or dynamic recompilation) layer like Intel's Software Development Emulator (SDE), or maybe QEMU. SDE is closed-source freeware, and very handy

问题 So I am learning how x86 works and have come across people saying that it is byte-addressable, yet can read words, double words, etc. How does the processor decide which method to use and when? E.g. for accessing the next instruction and when a user wants to read/write to memory, which addressing mode is used? 回答1: Every memory access has an operand-size specified by the machine-code instruction. (Addressing mode isn't the right term: different addressing modes are different ways of

问题 I have read that there are some registers that an x86 CPU cannot modify while in user mode (I believe these registers are called "privileged registers"). But can an x86 CPU read the values of these registers while in user mode, or is even reading not allowed? 回答1: All the registers you'd normally use for computation can be read/written in any mode (GP integer, x87/MMX, XMM/YMM/ZMM and AVX512 k0-7 mask registers), but there are many registers that are basically mode/control settings. Some

问题 According to the bit twiddling hacks website, the operation unsigned int a; // value to merge in non-masked bits unsigned int b; // value to merge in masked bits unsigned int mask; // 1 where bits from b should be selected; 0 where from a. unsigned int r; // result of (a & ~mask) | (b & mask) goes here r = a ^ ((a ^ b) & mask); allows to merge two bit sequences a and b according to a mask. I was wondering: Whether this operation had a specific/usual name? Whether specific assembly instruction

问题 According to the bit twiddling hacks website, the operation unsigned int a; // value to merge in non-masked bits unsigned int b; // value to merge in masked bits unsigned int mask; // 1 where bits from b should be selected; 0 where from a. unsigned int r; // result of (a & ~mask) | (b & mask) goes here r = a ^ ((a ^ b) & mask); allows to merge two bit sequences a and b according to a mask. I was wondering: Whether this operation had a specific/usual name? Whether specific assembly instruction

问题 In MIPS, a 32-bit jump instruction consists of 6-bits for the opcode and 26-bits for the target (destination) address that we want to set the program counter to. However, it is possible to set the program counter to a 28-bit target address. How is this possible if we can only fit 26-bits in the jump instruction? 回答1: Instructions on MIPS are always 4-byte aligned, so the low 2 bits of any valid target address can only be zero. Thus, the 26 bits specified in jump instructions are always

问题 I had this question on my exam and i am confused because as far as i know that move $t0, $a0 # COPY $A0 TO $T0 in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something? 回答1: Move is a pseudoinstruction, and when assembled will really be a different instruction. For instance move $t0, $zero gets implemented as addu $t0, $zero, $zero 来源： https://stackoverflow.com/questions/53286335/why-the-risc-instruction-sets-usually-do-not-contain-register-to-register-copy-i

问题 I notice that Intel Tremont has 64 bytes store instructions with MOVDIRI and MOVDIR64B. Those guarantees atomic write to memory, whereas don't guarantee the load atomicity. Moreover, the write is weakly ordered, immediately followed fencing may be needed. I find no MOVDIRx in IceLake. Why doesn't Ice Lake need such instructions like MOVDIRx ? (At the bottom of page 15) Intel® ArchitectureInstruction Set Extensions and Future FeaturesProgramming Reference https://software.intel.com/sites