gnu-make

Version number comparison inside makefile

穿精又带淫゛_ 提交于 2020-06-09 11:28:08
问题 In a makefile, I'd like to define a variable specifying whether the current redhat-release is greater than 5.3. (This variable will be passed to gcc as a #define) So far I've come up with: # Find out which version of Red-Hat we're running RH_VER_NUM = $(shell /bin/grep -o [0-9].[0-9] /etc/redhat-release) RH_GT_5_3 = $RH_VER_NUM > '5.3' What would be the correct way to define RH_GT_5_3? 回答1: GNU Make doesn't contain any string comparisons other than equality, and test can only do less-than

Version number comparison inside makefile

你离开我真会死。 提交于 2020-06-09 11:27:11
问题 In a makefile, I'd like to define a variable specifying whether the current redhat-release is greater than 5.3. (This variable will be passed to gcc as a #define) So far I've come up with: # Find out which version of Red-Hat we're running RH_VER_NUM = $(shell /bin/grep -o [0-9].[0-9] /etc/redhat-release) RH_GT_5_3 = $RH_VER_NUM > '5.3' What would be the correct way to define RH_GT_5_3? 回答1: GNU Make doesn't contain any string comparisons other than equality, and test can only do less-than

how to improve $(call $(eval $(call))) paradigm in using Make?

余生颓废 提交于 2020-05-18 03:46:08
问题 I write general makefiles and functions for users' convenience, so naturally they should have the simplest interfaces possible . When defining functions, I use this paradigm: define FUNCTION target: $1 endef FUNCTION2 = $(eval $(call FUNCTION,$1)) Now, instead of telling them to do this $(eval $(call FUNCTION, argument )) I can tell them to do this $(call FUNCTION2, argument ) which is simpler. This worked like a charm until somebody decided to use .EXPORT_ALL_VARIABLES , so that we have the

gnu make “Removing intermediate files”

南笙酒味 提交于 2020-05-14 19:13:23
问题 I have the following rules define compile_c $(ECHO) "CC $<" $(Q)$(CC) $(CFLAGS) -c -MD -o $@ $< @# The following fixes the dependency file. @# See http://make.paulandlesley.org/autodep.html for details. @# Regex adjusted from the above to play better with Windows paths, etc. @$(CP) $(@:.o=.d) $(@:.o=.P); \ $(SED) -e 's/#.*//' -e 's/^.*: *//' -e 's/ *\\$$//' \ -e '/^$$/ d' -e 's/$$/ :/' < $(@:.o=.d) >> $(@:.o=.P); \ $(RM) -f $(@:.o=.d) endef vpath %.c . $(TOP) $(BUILD)/%.o: %.c $(BUILD)/%.pp $

Why is make not deleting intermediate files?

試著忘記壹切 提交于 2020-03-23 07:42:28
问题 I'm having problems with GNU make 3.81 not deleting intermediate files. The issue is similar to GNU make Not Deleting Intermediate Files, but that answer doesn't solve my problem. I've distilled the issue to this test case: default: @echo no $@ target; exit 1 oncetwice: once twice @echo $@: $^ ## Uncommenting the following line is sufficient to cause GNU make 3.81 to ## not delete the intermediate 'twice.dep', even if it didn't exist ## previously (i.e., was created by this invocation).

GNU make is adding an extra step not in my Makefile that causes all sorts of linker errors. What's going on?

僤鯓⒐⒋嵵緔 提交于 2020-02-08 07:54:31
问题 Given the following makefile for GNU make: # TODOs so I don't forget: # - make debugging an option # - make 64 below an actual option # - figure out why make test seems to rebuild the DLL # - __declspec(dllimport) ifeq ($(MAKECMDGOALS),64) CC = x86_64-w64-mingw32-gcc RC = x86_64-w64-mingw32-windres mflag = -m64 else CC = i686-w64-mingw32-gcc RC = i686-w64-mingw32-windres mflag = -m32 endif OBJDIR = .objs OUTDIR = out BASENAME = wintable DLLFILE = $(OUTDIR)/$(BASENAME).dll LIBFILE = $(OUTDIR)/

Asan : Issue with asan library loading

血红的双手。 提交于 2020-02-06 07:56:03
问题 In our build system we have recently integrated ASAN tool (adding -fsanitize=address) to CFLAGS & also while linking , creating library .so files. Note:- We are using GCC 6.3 compiler. We are able to successfully build our code. But while running it fails with following issue: ==52215==ASan runtime does not come first in initial library list; you should either link runtime to your application or manually preload it with LD_PRELOAD. Here is my gcc command:- /local/common/pkgs/gcc/v6.3.0/bin

Makefile, Regex and multiple dependencies

做~自己de王妃 提交于 2020-02-02 05:18:09
问题 Assume the following files are in the same directory as the makefile: 01.1.dot 01.2.dot 02.1.dot 03.1.dot 03.2.dot 03.3.dot That means we have files of the form [0-9][0-9].[0-9].dot Furthermore, the makefile contains the following target: %.dot.tex: %.dot dot2tex <...> Now I would like to create a target which depend on files of the form [0-9][0-9].tex and they should also depend on all files of the form [0-9][0-9].*.dot.tex, such that the first two digits match. For example, make 03.pdf

Rule with static pattern fails

送分小仙女□ 提交于 2020-01-25 20:49:50
问题 I have a makefile to create HTML publication lists for different authors out of one BibTex file. The export is done using bibtex2html and works like a charm. But I'm stuck at the rule naming. I want to have the makefile as generic as possible to only adapt the results list when a new colleague starts or someone finishes his PhD. The workflow is the following: bib.bib is given Extract the publications from all authors in results into seperate files: `bib2bib -c 'author : "$*"' bib.bib' Now

Rule with static pattern fails

混江龙づ霸主 提交于 2020-01-25 20:49:22
问题 I have a makefile to create HTML publication lists for different authors out of one BibTex file. The export is done using bibtex2html and works like a charm. But I'm stuck at the rule naming. I want to have the makefile as generic as possible to only adapt the results list when a new colleague starts or someone finishes his PhD. The workflow is the following: bib.bib is given Extract the publications from all authors in results into seperate files: `bib2bib -c 'author : "$*"' bib.bib' Now