gnu-make

问题 How can I execute a shell script before building my targets in a Makefile, and see the output as it runs? I have a script called prepare.sh that generates a bunch of .pyx files. The .pyx files are the starting point of my build process involving make. It goes from .pyx -> .c -> .o -> .so I don't like having to run prepare.sh separately prior to make. I'd like make to run it for me. I got it to work but I don't see the output of the command. I'd like to see it. This is what I have now: PATH :=

问题 I have a GNU Makefile (version 3.81) that looks like the following: .PHONY: SPOneDot SPOneDot: ifndef X X=0.05 $$(info X undefined, changed to $X) endif ifndef Y Y=0.05 $$(info Y undefined, changed to $Y) endif python ./Submit3DSP.py -f OneDot.qdt -x $(X) -y $(Y) I execute with the following command line: make X=0.1 Y=0.1 SPOneDot but I get the following result: ifndef X make: ifndef: Command not found make: *** [SPOneDot] Error 127 I've looked in the makefile documentation and seen others

问题 I can set number of threads for the build process using -j argument. For example, I have 4 cores +4 virtual. When I write: make -j8 the speed increases 4 times. Is it possible to set that value as default? (For example, in Linux Gentoo, in config file, it's possible to set this default value). p.s. I have Arch Linux 回答1: Your question is not about threads, but processes (jobs) executed by make. The simple, way to set this, when make is used from the console is adding: alias make="/usr/bin

问题 I can set number of threads for the build process using -j argument. For example, I have 4 cores +4 virtual. When I write: make -j8 the speed increases 4 times. Is it possible to set that value as default? (For example, in Linux Gentoo, in config file, it's possible to set this default value). p.s. I have Arch Linux 回答1: Your question is not about threads, but processes (jobs) executed by make. The simple, way to set this, when make is used from the console is adding: alias make="/usr/bin

问题 I'm trying to have a makefile variable for the content of a directory after that directory has been updated by a recipe. Why does this not work : A_FILE = $(wildcard subdir/*) all: a @echo $(A_FILE) a: @mkdir ./subdir @touch subdir/b @touch a $ rm -rf ./subdir && make $ ...whereas this does: A_FILE = $(wildcard subdir/*) all: a @echo $(A_FILE) a: subdir/b @touch a subdir/b: @mkdir ./subdir @touch subdir/b $ rm -rf ./subdir && make subdir/b $ ? I thought lazy-evaluation meant the variable was

问题 Below is the folder structure for my code. This is a very small example to understand the concept of multiple makefiles based on which I have to create makefile for bigger code structure. work ├── code | | | └── main.h and test.h files here │ └── main.c and test.c files here | └── subdir.mk | ├── _Build/ │ └── Makefile here I am keeping both Makefile and subdir.mk files to be very basic and simple to grasp the concept. Below is the code for subdir.mk #subdir.mk #==============================

问题 I have a repository that uses python scripts and a Makefile. I want to have a setup procedure that allows them to easily set up an environment and copy in the necessary data files from our server. The problem with including the source data files in the Makefile is that the company server uses spaces in the drive name, which make doesn't like very much, so I can list those files as dependencies for the target output file. My current Makefile basically does only the following: .PHONY : all all

问题 I have the following Makefile SHELL=/bin/bash .SHELLFLAGS=-O extglob -o errexit -o pipefail -o nounset -c .PHONY: testing define getFileContents $(shell cat ./test.txt) endef TEST_STATIC=dummy deploy: $(eval TEST=$(getFileContents)) @echo "$(TEST)" ifeq ($(TEST),dummy) @echo "$(TEST) is FAILED" else @echo "$(TEST) is PASS" endif ifneq (,$(findstring dummy,$(TEST))) @echo "$(TEST) is FAILED" else @echo "$(TEST) is PASS" endif ifeq ($(TEST_STATIC),dummy) @echo "$(TEST) is FAILED" else @echo "$

问题 I downloaded GNU make 4.2.1 from here (make-4.2.1.tar.gz) and installed it following the instruction found in the INSTALL file that is present in the expanded folder. Now I run make -v in the shell and I still get that the system sees the old version: GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. This program built for i386

问题 This question is a follow-up to What makefile lazy evaluation rule governs this behavior?. I'm still trying to grok some of the rules of gnu make's lazy evaluation. I want to have a make variable for the content of a directory after that directory has been updated by a recipe. This Makefile demonstrates that $(A_FILE) is evaluated to find the created file when it's in the "parent" of the recipe that actually creates the file: A_FILE = $(wildcard subdir/*) all: a @echo $(A_FILE) a: @mkdir .