ghdl

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 So i have a task to do the mod operation between 2 vectors(called here dividendo and divisor), so what i need is dividendo mod divisor. We have some restrictions on this code, that is, we cant use iee_std_logic_1164, textio, etc. I think the only libraries allowed are IEEE and IEEE.numeric_bit The algorithm to this operation tells me to: while(dividendo >= divisor){ dividendo = dividendo - divisor } return dividendo And then i wrote this vhdl file: library IEEE; entity resto is port (clock ,

问题 I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks i_m50_clk :in std_logic; i_m50_rst :in std_logic; -- APB Command Inteface s_paddr :in std_logic_vector(31 downto 0); s_psel :in std_logic; s_penable :in std_logic; s_pwrite :in std_logic; s_pwdata :in std_logic_vector(31 downto 0); s_pready :out std_logic; s_prdata

问题 I'm trying to construct a ROM, which has as declaration a : in std_logic_vector(5 downto 0) for the access address. My problem its that I don't know how to access the ROM array with a std_logic_vector, Should I use a cast to integer or what else can I do? My code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------------------------------------------------- entity imem is GENERIC(CONSTANT N : INTEGER := 32); port (a : in std_logic_vector

问题 I'm using a PowerShell script to control different compilation steps of an compiler (ghdl.exe). The compiler has 3 different output formats: No output and no error => $LastExitCode = 0 outputs on stderr (warnings), but no errors => $LastExitCode = 0 outputs on stderr (errors), and maybe warnings => $LastExitCode != 0 Because handling of stderr and stdout seams to be very buggy, I used the method presented in this StackOverflow post: PowerShell: Manage errors with Invoke-Expression Here is my

问题 i just wrote a simple VHDL program. I saved the file as a .vhd file. Then I compiled it with ghdl -a test.vhd and then built and executable file with ghdl -e test And finally tried to run it with ghdl -r test What happened is that I now have a work-obj93.cf file that is visible and two other files, namely .. and . that are somehow invisible. Can someone tell how exactly I can test a vhdl program on my Mac? Maybe in in combination with GTKWave. 回答1: That as they say is a big ask! There's a